International Business Machines Corporation patent applications on June 27th, 2024
Patent Applications by International Business Machines Corporation on June 27th, 2024
International Business Machines Corporation: 46 patent applications
International Business Machines Corporation has applied for patents in the areas of H01L23/528 (7), H01L29/06 (5), H01L29/423 (4), H01L29/417 (4), H01L29/08 (4) G06N20/00 (2), H01L27/092 (2), B25J9/1671 (1), H01L29/0665 (1), H01L21/76843 (1)
With keywords such as: data, device, layer, contact, region, based, image, source, user, and chip in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Akash U. Dhoot of Pune (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Saraswathi Sailaja Perumalla of Visakhapatnam (IN) for international business machines corporation, Venkata Ratnam Alubelli of Visakhapatnam (IN) for international business machines corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1671
Abstract: a processor may receive environment data associated with a robotic device in an environment. the processor may analyze the environment data to identify one or more activities the robotic device may perform in the environment. the processor may generate one or more simulations associated with the one or more activities and the robotic device. the processor may determine one or more limitations of the robotic device associated with the one or more activities. the processor may identify, responsive to determining one or more limitations, one or more apparatuses. the one or more apparatuses may be associated with the one or more limitations.
Inventor(s): Jeremy R. FOX of Georgetown TX (US) for international business machines corporation, Randy A. RENDAHL of Raleigh NC (US) for international business machines corporation, Mauro MARZORATI of Lutz FL (US) for international business machines corporation, Sarbajit K. RAKSHIT of Kolkata (IN) for international business machines corporation
IPC Code(s): B29C64/188, B22F10/60, B22F10/73, B22F10/85, B23K26/16, B23K26/361, B29C64/357, B29C64/393, B33Y10/00, B33Y40/20, B33Y50/02
CPC Code(s): B29C64/188
Abstract: a system and methods for enhanced printing to manufacture 3d objects implement optimized utilization of additive printing and subtractive laser beam machining, enabling enhanced, efficient and effective manufacturing of 3d objects. dynamically allocating the operations and the sequence of operations between additive printing and laser beam machining for each layer of a 3d object being manufactured enables optimizing manufacturing time, power consumption, and material consumption to manufacture 3d objects.
Inventor(s): Mauro MARZORATI of Lutz FL (US) for international business machines corporation, Faith OPIYO of Nieuw Vennep (NL) for international business machines corporation, Jeremy R. FOX of Georgetown TX (US) for international business machines corporation, Vinod A. VALECHA of Pune (IN) for international business machines corporation
IPC Code(s): B29C64/40, B29C64/176, B29C64/236, B29C64/245, B29C64/321, B29C64/35, B29C64/393, B33Y10/00, B33Y30/00, B33Y40/20, B33Y50/02, B65G47/90
CPC Code(s): B29C64/40
Abstract: a disclosed system and methods provide enhanced, continuous 3d printing to manufacture 3d objects utilizing stabilizers supporting a 3d object being printed in components along a conveyor belt, enabling enhanced, efficient and effective manufacturing of 3d objects. a selected 3d object is printed from a primary material on supporting stabilizers, and the stabilizers are printed from a secondary material. the system coordinates movement of the printer head along the printing plane and the conveyor belt, creating an elongated printing surface along the conveyor belt for continuous 3d printing. upon completion, the 3d object with the supporting stabilizers exits the conveyor belt and the 3d object is removed from the stabilizers.
Inventor(s): Matthew Beck of Danbury CT (US) for international business machines corporation
IPC Code(s): G01R33/035, G06N10/00, G06N10/40, H03F19/00, H03K3/38, H03K5/00, H03K17/92, H10N60/12
CPC Code(s): G01R33/0358
Abstract: a radio-frequency (rf) to direct current (dc) converter is provided. when a dc electrical current is applied via a dc input port of the converter, the dc electrical current is shunted to ground through a josephson junction (jj) of the converter and substantially no dc electrical current flows through a resistor of the converter, and when an rf electrical current is applied via an rf input port of the converter, output trains of sfq current pulses from a dc to sfq converter of the rf-to-dc converter with pulse-to-pulse spacing inversely proportional to the rf electrical current frequency cause the jj to switch at a rate commensurate with an rf frequency of the rf electrical current to generate a steady state voltage across the jj linearly dependent on the rf frequency.
Inventor(s): Bao Zhang of Beijing (CN) for international business machines corporation, Jing Lu of Beijing (CN) for international business machines corporation, Dong Hui Liu of Beijing (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Xiao Yan Tang of Beijing (CN) for international business machines corporation, Yong Yin of Beijing (CN) for international business machines corporation, Jia Yu of Beijing (CN) for international business machines corporation
IPC Code(s): G06F8/41, G06F8/71, G06F9/54
CPC Code(s): G06F8/433
Abstract: in a first aspect of the invention, there is a computer-implemented method including: generating, by one or more processors, dependency version information for a target software application, based on activity of a compiler registered with an event handler; generating, by the one or more processors, one or more dependency sections with a dependency list for the target software application, wherein the dependency list incorporates the dependency version information; and building, by the one or more processors, a software package with the one or more dependency sections with the dependency list for the target software application.
Inventor(s): Amar Shah of PUNE (IN) for international business machines corporation, Akash Chandra of Bengaluru (IN) for international business machines corporation, Prashant Farkya of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F8/61
CPC Code(s): G06F8/63
Abstract: an example operation may include one or more of receiving a request to build an instance of a container image that comprises a plurality of image layers, wherein the request comprises a tag identifier, creating the container image comprising the plurality of image layers, identifying a subset of image layers from among the plurality of image layers within the container image to exclude based on the tag identifier, and pulling remaining image layers from the container image with the subset of image layers excluded therefrom to an instance of a container deployed in a runtime environment.
Inventor(s): Scott B. COMPTON of Hyde Park NY (US) for international business machines corporation, Elpida TZORTZATOS of Lagrangeville NY (US) for international business machines corporation, Purvi Sharadchandra PATEL of Rock Hill SC (US) for international business machines corporation, Christine Michele YOST of Hopewell Junction NY (US) for international business machines corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0778
Abstract: techniques for selective memory dumping based on tracking memory use. for each set of contiguous frames of memory, whether a reference bit is set is determined. the reference bit is included in a control field of a frame of the respective set. each set has an associated mapping from corresponding pages of a virtualized address space. an unreferenced-interval count is maintained for the respective set. the unreferenced-interval count represents an age since any frame of the respective set was last accessed. the unreferenced-interval count and the reference bit are cleared upon determining that the reference bit is set. if the unreferenced-interval count of a set does not exceed a threshold count, the set is included in a diagnostic dump of the memory when a condition for generating the diagnostic dump is met.
Inventor(s): Madhavi Rani of Hyderabad (IN) for international business machines corporation, Avneet Kaur Nanda of Delhi (IN) for international business machines corporation, Pravin Kailashnath Kedia of Mumbai (IN) for international business machines corporation, Abhishek Jain of Baraut (IN) for international business machines corporation
IPC Code(s): G06F11/07, G06F11/34
CPC Code(s): G06F11/079
Abstract: intelligent logging of microservice failures is provided. it is predicted that failure of a microservice in a microservice chain will occur during a predicted high-risk failure period for a predicted failure type while performing a transaction corresponding to an application. a detailed logging level is determined for the microservice to record sufficient information to identify a root cause of the failure of the microservice for the predicted failure type. the microservice is directed to increase a current logging level of the microservice to the detailed logging level during the predicted high-risk failure period to record sufficient information to identify the root cause of the failure of the microservice.
Inventor(s): VIKAS CHANDRA of BANGALORE (IN) for international business machines corporation, SARIKA SINHA of BANGALORE (IN) for international business machines corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3664
Abstract: an example operation may include one or more of tracking debugging actions performed to a software system via a runtime environment of the debugging actions, identifying one or more debugging attributes of an object of the software system based on the tracked debugging actions performed to the software system, generating a window which includes details of the one or more identified debugging attributes of the object, and displaying the window which includes the details of the one or more identified debugging attributes via a user interface of a debugging program.
Inventor(s): Derek E. WILLIAMS of Round Rock TX (US) for international business machines corporation, Luke MURRAY of Austin TX (US) for international business machines corporation, Guy L. GUTHRIE of Austin TX (US) for international business machines corporation, Hugh SHEN of Round Rock TX (US) for international business machines corporation
IPC Code(s): G06F12/0802, G06F9/54, G06F12/10
CPC Code(s): G06F12/0802
Abstract: a data processing system includes a master, a central request agent, and a plurality of snoopers communicatively coupled to a system fabric for communicating requests subject to retry. the master issues on the system fabric a multicast request intended for the plurality of snoopers. the central request agent receives the multicast request on the system fabric, assigns the multicast request to a particular state machine among a plurality of state machines in the central request agent, and provides the master a coherence response indicating successful completion of the multicast request. the central request agent repetitively issues on the system fabric a multicast request in association with a machine identifier identifying the particular state machine until a coherence response indicates the multicast request is successfully received by all of the plurality of snoopers.
Inventor(s): Dong Hui Liu of Beijing (CN) for international business machines corporation, Jing Lu of Beijing (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Naijie Li of Beijing (CN) for international business machines corporation, Xiao Yan Tang of Beijing (CN) for international business machines corporation, Bao Zhang of Beijing (CN) for international business machines corporation, Jun Su of Beijing (CN) for international business machines corporation, Yong Yin of Beijing (CN) for international business machines corporation, Jia Yu of Beijing (CN) for international business machines corporation
IPC Code(s): G06F12/1009, G06F12/0882, G06F12/1027
CPC Code(s): G06F12/1009
Abstract: a method, including: monitoring resource utilization of an operating system (os) with applications utilizing larger pages; determining the monitored resource utilization is greater than a threshold resource utilization; in response to the determining the monitored resource utilization is greater than a threshold resource utilization, determining a respective larger pages index value for each of the applications utilizing larger pages; and turning off larger pages utilization of a subset of the applications utilizing larger pages, wherein the subset comprises a predefined number of the applications utilizing larger pages that have highest determined larger pages index values.
Inventor(s): Geoffrey Burr of Ossining NY (US) for international business machines corporation, Shubham Jain of Elmsford NY (US) for international business machines corporation, Yasuteru Kohda of Yamato-shi (JP) for international business machines corporation, Milos Stanisavljevic of Langnau am Albis (CH) for international business machines corporation
IPC Code(s): G06F17/16, G06N3/063
CPC Code(s): G06F17/16
Abstract: systems and methods for performing layer normalization are described. a circuit can receive a sequence of input data across a plurality of clock cycles, where the sequence of input data represents a portion of an input vector. the circuit can determine a plurality of sums and a plurality of sums of squares corresponding to the sequence of input data. the circuit can determine, based on the plurality of sums of squares, a first scalar representing an inverse square-root of a variance of vector elements in the input vector. the circuit can determine a second scalar representing a negation of a product of the first scalar and a mean of the vector elements in the input vector. the circuit can determine, based on the first scalar, the second scalar and the received sequence of input data, an output vector that is a normalization of the input vector.
20240211586.PROMPTING DATA SESSION_simplified_abstract_(international business machines corporation)
Inventor(s): Harish BHARTI of PUNE (IN) for international business machines corporation, Pinaki BHATTACHARYA of PUNE (IN) for international business machines corporation, Sandeep SUKHIJA of RAJASTHAN (IN) for international business machines corporation, Dinesh WADEKAR of PUNE (IN) for international business machines corporation, Simmi GUPTA of GHAZIABAD (IN) for international business machines corporation, Rajesh Kumar SAXENA of THANE EAST (IN) for international business machines corporation
IPC Code(s): G06F21/51
CPC Code(s): G06F21/51
Abstract: methods, computer program products, and systems are presented. the method computer program products, and systems can include, for instance: examining user data of at least one user to determine whether a criterion has been satisfied for running a prompting data session for prompting the at least one user; responsively to determining that the criterion has been satisfied for running the prompting data session for prompting the at least one user, running a prompting data session, wherein the running the prompting data session includes (a) establishing and iteratively updating a relationship graph and (b) presenting the iteratively updated relationship graph to one or more user.
Inventor(s): Marina Milazzo of Sugar Hill GA (US) for international business machines corporation, Mauricio Zamora Peralta of Naranjo (CR) for international business machines corporation, STEPHEN KYLE TIBBETTS of Rockmart GA (US) for international business machines corporation, ERIC Daniel HANRATTY of San Jose (CR) for international business machines corporation, Alex Chaves Malaver of San Jose (CR) for international business machines corporation, JASON HARTLEY of Atlanta GA (US) for international business machines corporation, James F. McGarry of HADDONFIELD GA (US) for international business machines corporation, Mahbod Tavallaee of Arlington MA (US) for international business machines corporation, Jose Arturo Maroto Picado of San Jose (CR) for international business machines corporation, Marvin Andres Valerio Gonzalez of San Jose (CR) for international business machines corporation, David Michael McGinnis of Roswell GA (US) for international business machines corporation
IPC Code(s): G06F21/55
CPC Code(s): G06F21/554
Abstract: an approach is disclosed for assessing effectiveness of security information and event management (siem) environments. a rule status information with a number of used rules and a number of unused rules and a log source status with a number of active log sources and a number of inactive log sources is received from a threat detection insight (tdi) component by a production siem environment assessment report (spear) tool. tdi performance scores and tdi quality scores are received from the tdi component for each used rule by the spear tool. the spear tool determines an availability score, a performance score, and a quality score from the rule status information, the log source status information, the tdi performance scores, and the tdi quality scores. the spear tool determines a spear from the availability score, the performance score, and the quality score.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Sathya Santhar of Ramapuram (IN) for international business machines corporation, Sridevi Kannan of Katupakkam (IN) for international business machines corporation
IPC Code(s): G06F30/27
CPC Code(s): G06F30/27
Abstract: a system and method of automatically generating product designs is provided. in embodiments, methods include converting a digital twin model of a physical product having a primary design to a virtual digital twin model enabling user interactions with features of the virtual digital twin model in a virtual environment; collecting user interaction data generated from virtual interactions of users with the features of the virtual digital twin model in the virtual environment; generating sentiment data indicating a sentiment of the users associated with the virtual interactions of the users with the features of the virtual digital twin model; and inputting the user interaction data, the sentiment data, and different groups of the users into a trained machine learning (ml) predictive model, thereby generating, as an output of the ml predictive model, a different secondary design of the physical product for each of the different groups of users.
Inventor(s): Zhong Fang Yuan of Xi'an (CN) for international business machines corporation, Tong Liu of Xi'an (CN) for international business machines corporation, Li Ni Zhang of Beijing (CN) for international business machines corporation, Wei Ting Hsieh of Tainan (TW) for international business machines corporation, Huan Meng of Wuhan (CN) for international business machines corporation, Qi Liang Zhou of Xi'an (CN) for international business machines corporation, Jia Wei He of Xi'an (CN) for international business machines corporation, Yi Fan Liu of Beijing (CN) for international business machines corporation, Lin Ji of Chengdu (CN) for international business machines corporation
IPC Code(s): G06N3/042
CPC Code(s): G06N3/042
Abstract: a computer-implemented process for training a neural network having a plurality of transform layers includes the following operations. input data for one transform layer of the plurality of transform layers is transformed by the one transform layer into output data. a neural-backed decision tree is generated for the transform layer, a neural-backed decision tree. the transforming and the generating are repeated for each of the plurality of transform layers. a neural-backed decision tree map for a particular one of the plurality of transform layers maps output data of the particular one of the plurality of transform layers into a list of interpretable words from a generative search domain of facts and evidence.
Inventor(s): Kevin Eykholt of White Plains NY (US) for international business machines corporation, Wenbo Guo of State College PA (US) for international business machines corporation, Taesung Lee of Ridgefield CT (US) for international business machines corporation, Jiyong Jang of Chappaqua NY (US) for international business machines corporation
IPC Code(s): G06N3/08, G06N3/047
CPC Code(s): G06N3/08
Abstract: safety verification for reinforcement learning can include receiving a policy generated by deep reinforced learning, where the policy is used in acting in an environment having a set of states. responsive to determining that the policy is a non-deterministic policy, the non-deterministic policy can be decomposed into a set of deterministic policies. responsive to determining that a state-transition function associated with the set of states is unknown, the state-transition function can be approximated at least by training a deep neural network and transforming the deep neural network into a polynomial. using a constraint solver the policy with the state-transition function can be verified. runtime shielding can be performed.
Inventor(s): Lan Ngoc Hoang of Timperley (GB) for international business machines corporation, Alexander Zadorojniy of Haifa (IL) for international business machines corporation
IPC Code(s): G06N3/092
CPC Code(s): G06N3/092
Abstract: a method and system of increasing interpretability of decision making methods include a network module providing raw data from an environment to a machine learning (ml) module. in response to the raw data being delivered to the ml module, the ml module generates a trained classifier using the raw data. a pruning module then prunes a plurality of dominant variables, in the sense of being most relevant for the decision made with respect to the classifier, using the trained classifier. the network module then provides the sub-optimal policy to a reinforcement learning (rl) module, where a generated sub-optimal policy is applied to the environment to obtain a dataset by applying the sub-optimal policy and generating a trajectory. the ml module then generates an interpretable set of rules using the generated trajectory.
Inventor(s): Lam Minh Nguyen of Ossining NY (US) for international business machines corporation, Wang Zhang of Cambridge MA (US) for international business machines corporation, Subhro Das of Cambridge MA (US) for international business machines corporation, Alexandre Megretski of Acton MA (US) for international business machines corporation, Luca Daniel of Cambridge MA (US) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: providing a trained reinforcement learning (rl) model by formulating a decision process problem for the rl model, defining at least one of a logarithmic loss function for the rl model and defining an initiation point for the rl model according to an optimized spectral norm of the rl model, training the system according to the logarithmic loss function or from the initiation point, and providing the trained rl model.
Inventor(s): Anna Yanchenko of Groton MA (US) for international business machines corporation, Wesley M. Gifford of Ridgefield CT (US) for international business machines corporation, Brian Leo Quanz of Yorktown Heights NY (US) for international business machines corporation, Nam H. Nguyen of Pleasantville NY (US) for international business machines corporation, Pavithra Harsha of Pleasantville NY (US) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: mechanisms are provided for automatic identification of a reconciliation computer tool for producing coherent reconciled data from base data generated by a computer model. a machine learning training operation is executed on one or more performance prediction computer model(s) (ppcms) based on first input features of at least one hierarchical dataset, and second input features of a plurality of different reconciliation computer tools. the ppcm(s) generate a prediction of performance of a corresponding reconciliation computer tool based on the first and second input features. features are extracted from a runtime hierarchical dataset and input into the trained ppcm(s) which generate predictions of performance of a plurality of reconciliation computer tools based on the extracted features of the runtime hierarchical dataset. the reconciliation computer tools are ranked relative to one another based on the predictions of performance. an output is generated based on the ranking of the reconciliation computer tools.
Inventor(s): Anna Yanchenko of Groton MA (US) for international business machines corporation, Wesley M. Gifford of Ridgefield CT (US) for international business machines corporation, Brian Leo Quanz of Yorktown Heights NY (US) for international business machines corporation, Nam H. Nguyen of Pleasantville NY (US) for international business machines corporation, Pavithra Harsha of Pleasantville NY (US) for international business machines corporation
IPC Code(s): G06Q10/0631
CPC Code(s): G06Q10/06313
Abstract: mechanisms are provided for performing automated and dynamic reconciliation of forecasts for hierarchical datasets. a machine learning training is executed on a dynamic reconciliation computer model engine to train the dynamic reconciliation computer model engine, based on historical data and forecast data, to learn an association of reconciliation computer models with structural changes in a hierarchical dataset. runtime forecast data is generated based on a runtime hierarchical dataset, and the trained dynamic reconciliation computer model engine is executed on the runtime forecast data to reconcile the runtime forecast data across a hierarchy of the runtime forecast data. the trained dynamic reconciliation computer model applies different reconciliation computer models to the runtime forecast data based on structural changes in the runtime forecast data. reconciled runtime forecast data is generated based on results of executing the trained dynamic reconciliation computer model engine on the runtime forecast data, which is then output.
Inventor(s): Krishnasuri Narayanam of Bangalore (IN) for international business machines corporation, VENKATRAMAN RAMAKRISHNA of Bangalore (IN) for international business machines corporation, Dhinakaran Vinayagamurthy of Erode (IN) for international business machines corporation, Sandeep Nishad of Bangalore (IN) for international business machines corporation, VINAYAKA PANDIT of Bangalore (IN) for international business machines corporation
IPC Code(s): G06Q40/03, G06Q20/40
CPC Code(s): G06Q40/03
Abstract: a computer-implemented method for automatically and digitally securing an asset is disclosed. the computer-implemented method includes hashing a secret preimage to produce a secret hash. the computer-implemented method further includes locking a digital collateral asset with the secret hash for a first predetermined period of time. the computer-implemented method further includes locking a digital loan asset with the secret hash for a second predetermined period of time, wherein the second predetermined period of time is less than the first predetermined period of time. the computer-implemented method further pledging a digital loan repayment up to the amount of time of the first predetermined period of time plus the second predetermined period of time. the computer-implemented method further includes responsive to receiving a pledge for the digital loan repayment, automatically unlocking the digital collateral asset for a borrower of the digital loan asset.
Inventor(s): Christian Compton of Austin TX (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06Q50/30, G06F18/22, G06Q10/083, G06Q10/0833, G06Q10/087, G06Q30/0601
CPC Code(s): G06Q50/30
Abstract: dynamic shopping that includes receiving, at a system, an order for a selected product for purchasing and a package pickup location from a device of a user. the method can further include determining a type of product the user has ordered for pick up at the package pickup location, and the method can use the system for dynamic shopping to determine other products for potential order at the pickup location. the computer implemented method can also add to the order other products for potential order.
Inventor(s): Peter Christopher Gramenides of Kingston NY (US) for international business machines corporation, Vijai Kalathur of Wappingers Falls NY (US) for international business machines corporation, Michael Andrasak of Red Hook NY (US) for international business machines corporation, Ashish Deshpande of Hopewell Junction NY (US) for international business machines corporation, Peter J. Rooney of Poughquag NY (US) for international business machines corporation, Gary R. Picher of Wappingers Falls NY (US) for international business machines corporation
IPC Code(s): G06V10/762, G06V10/75, G06V10/778
CPC Code(s): G06V10/762
Abstract: a computer hardware system includes a processor including a comparison engine and configured to perform the following executable operations. using the comparison engine, each image in a dataset of highly-similar images is compared to every other image in the dataset of highly-similar images to generate a comparison score for each image-image pair. the images in the dataset of highly-similar images are clustered into a plurality of image clusters based upon the comparison scores. one of the plurality of image clusters is selected as representing an original image. a data processing operation is performed on the dataset of highly-similar images based upon the selection of the one of the plurality of image clusters as representing the original image.
Inventor(s): Andrew GENG of Madison WI (US) for international business machines corporation, Pin-Yu CHEN of White Plains NY (US) for international business machines corporation
IPC Code(s): G06V10/774, G06F40/284, G06V10/80, G06V20/62
CPC Code(s): G06V10/774
Abstract: techniques to fine-tune a joint text-image encoder via model reprogramming. the joint text-image encoder includes an image encoder and a text encoder, which are trained. an image and a caption describing the image are received. a reprogrammed image is generated based on the received image and using a first function. a reprogrammed caption is generated based on the received caption and using a second function. the image encoder and the text encoder are further trained using the reprogrammed image and the reprogrammed caption. one or more parameters for each of the first and second functions are backpropagated to produce, via transfer learning, the fine-tuned joint text-image encoder.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Shailendra Moyal of Pune (IN) for international business machines corporation
IPC Code(s): G09G5/10, G06T19/00, G06T19/20
CPC Code(s): G09G5/10
Abstract: a computer-implemented method, according to one embodiment, includes learning a rate of eye adaptation that a first user's pupil muscle adjusts. in response to a determination that the first user is moving from a first location having a first level of light illumination to a second location having a second level of light illumination, it is determined whether a difference in the levels has a potential for causing eye adaptation issues for the first user. in response to a determination that the difference in the levels has a potential for causing eye adaptation issues, a level of light illumination that will allow the first user's pupil muscle to adjust at the learned rate of eye adaptation is determined. a first representation of the second location is output for display on a mixed reality device worn by the first user upon the first user entering the second location.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Willie Lester Muchrison, JR. of Troy NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L21/76843
Abstract: a semiconductor interconnect structure and formation thereof. the semiconductor interconnect structure includes a first high aspect ratio metal line. the first high aspect ratio metal line includes a first low aspect ratio line segment and a second low aspect ratio line segment.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Scott A. DeVries of Albany NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L21/768, H01L21/311, H01L23/528, H01L23/532
CPC Code(s): H01L21/76879
Abstract: a chip is manufactured using a method for forming a back-end-of-line (beol) layer on an ic chip surface comprises providing a first layer on top of a substrate layer of the ic chip, the first layer comprising a bottom portion of a metallic fill region having a first width as seen in a vertical cross-section of the ic chip. the method further provides a second layer on top of the first layer. the second layer comprises a middle portion of the metallic fill region having a second width that is wider than the bottom portion of the metallic fill region. the method provides a third layer on top of the second layer. the third layer comprises a top portion of the metallic fill region having a third width as seen in the vertical cross-section of the ic chip that is narrower than the middle portion of the metallic fill region.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/8234, H01L23/528, H01L27/06, H01L29/06
CPC Code(s): H01L23/5223
Abstract: semiconductor structures, devices and methods of fabricating the same, including a semiconductor device that includes a backside power rail (bspr), a source-drain (s/d) region connected to the bspr, and a metal-insulator-metal capacitor (mimc), where the bspr directly connects to the mimc by a mimc via for backside power rail (vbpr) metal contact.
Inventor(s): David Michael Audette of Colchester VT (US) for international business machines corporation, Grant Wagner of Jericho VT (US) for international business machines corporation, Steven Paul Ostrander of Poughkeepsie NY (US) for international business machines corporation, Hubert Harrer of Schoenaich (DE) for international business machines corporation, Arvind Kumar of Chappaqua NY (US) for international business machines corporation, Thomas Anthony Wassick of LaGrangeville NY (US) for international business machines corporation, Matthew Sean Grady of Burlington VT (US) for international business machines corporation, Sungjun Chun of Austin TX (US) for international business machines corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/538, H01L25/00
CPC Code(s): H01L25/0655
Abstract: an apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. the array of micro-bumps includes a plurality of subarrays of micro-bumps. micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. the apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. the card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. in some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.
Inventor(s): Shravana Kumar Katakam of Lehi UT (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Indira Seshadri of Niskayuna NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L23/50, H01L23/522, H01L29/08, H01L29/66
CPC Code(s): H01L27/092
Abstract: a microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. a first conductive contact is in contact with a top surface and side surface of the first source and drain structure. a second conductive contact is in contact with a top surface and side surface of the second source and drain structure. the second conductive contact includes a via extension to connect to a backside component. a separating layer is located between the first conductive contact and the second conductive contact. a first sidewall of the separating layer is flush with the first conductive contact. a second sidewall of the separating layer is flush with the second conductive contact.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L23/528, H01L29/08, H01L29/417, H01L29/78
CPC Code(s): H01L27/092
Abstract: embodiments of the invention provide a multi-layer integrated circuit (ic) structure that includes a cell having a cell boundary defined by a plurality of transistor-gate pitch (tgp) regions and an in-line contact region. the plurality of tgp regions include a reduced-area tgp region and non-reduced area tgp regions. the reduced-area tgp region is less than each of the non-reduced-area tgp regions. an in-line contact is within the in-line contact region and operable to electrically couple to a source or drain (s/d) region within the in-line contact region.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L23/535, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/0922
Abstract: a semiconductor structure including stacked transistor structures each including a top device stacked directly above a bottom device, and a placeholder dielectric and a backside gate contact within a dielectric capping layer beneath the stacked transistor structures, where the placeholder dielectric is directly below a first bottom source drain region, and the backside gate contact is directly below a second bottom source drain region.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L27/118, H03K17/693
CPC Code(s): H01L27/11807
Abstract: integrated circuits and related logic circuits and structures employing vtfet logic devices. in particular, during middle-of-line (mol) processing, method steps are employed for forming two-level mol contact connector structures below first (m1) metallization level wiring formed during subsequent beol processing. using damascene and subtractive metal etch techniques, respective mol contact connector structures at two levels are formed with a second level above a first level contact. these contact connector structures at two levels below m1 metallization level can provide cross-connections to vtfet devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access. the flexible mol cross-connections made below m1 metallization level provides for much improved m1 and m2 wirability and enable semiconductor circuit layouts that allow for improved cell size reduction without creating significant connection issues at high wiring levels thereby increasing circuit design flexibility.
Inventor(s): Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Andrew M. Greene of Slingerlands NY (US) for international business machines corporation, Curtis S. Durfee of Schenectady NY (US) for international business machines corporation, Oleg Gluschenkov of Tannersville NY (US) for international business machines corporation, Andrew Gaul of Halfmoon NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L29/08, H01L29/10, H01L29/423
CPC Code(s): H01L29/0665
Abstract: a semiconductor structure includes a gate region, a source/drain region, and a nanosheet semiconductor layer extending continuously across the gate region and the source/drain region. the nanosheet semiconductor layer includes a first portion in the gate region and a second portion in the source/drain region. the source/drain region includes a cladded epitaxial layer wrapping around the second portion of the nanosheet semiconductor layer.
Inventor(s): Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Robert Robison of Rexford NY (US) for international business machines corporation, Mohammad Hasanuzzaman of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L29/10, H01L27/092, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/1054
Abstract: a semiconductor device includes a first stacked structure and a second stacked structure disposed on a substrate. the first stacked structure comprises a first plurality of gate structures alternately stacked with a first plurality of channel layers, and the second stacked structure comprises a second plurality of gate structures alternately stacked with a second plurality of channel layers. a first plurality of epitaxial source/drain regions are disposed on sides of the first stacked structure, and a second plurality of epitaxial source/drain regions are disposed on sides of the second stacked structure. a first dielectric layer is disposed between the first stacked structure and the substrate, and between the first plurality of epitaxial source/drain regions and the substrate. a second dielectric layer is disposed between the second stacked structure and the substrate. at least a portion of the second plurality of epitaxial source/drain regions contact the substrate.
Inventor(s): Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L23/528
CPC Code(s): H01L29/41758
Abstract: a semiconductor device includes at least a direct backside contact between a source line and a source epitaxial growth and/or a drain line and a drain epitaxial growth. a clock signal line contact via can connect a gate to a backside clock signal line. the clock signal line contact via is surrounded by a deep sti fill to prevent shorting between the clock signal line and the source and/or drain lines in the backside power rail.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Nicolas Jean Loubet of Guilderland NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L23/528, H01L29/06, H01L29/40, H01L29/423, H01L29/775
CPC Code(s): H01L29/41766
Abstract: a semiconductor device includes a transistor device, including a source and drain region, and a gate region. a bottom dielectric isolation layer is on a backside of the transistor device. a buffer layer is on a backside of the bottom dielectric isolation layer. a first conductive contact is positioned on a backside of the transistor device in contact with a backside of the source and drain region, through the bottom dielectric isolation layer and through the buffer layer. a second conductive contact is in contact with the gate region from a frontside of the gate region.
Inventor(s): Krishnan VENKITASUBRAMANIAN of Bengaluru (IN) for international business machines corporation, Ramakrishna ALAVALA of Podili (IN) for international business machines corporation, Sundaragopal VENKATRAMAN of Chennai (IN) for international business machines corporation
IPC Code(s): H04L41/08, G06F40/279, G06F40/30, H04L41/0893
CPC Code(s): H04L41/0879
Abstract: a method includes: determining, by a processor set, a service availability impact and a user tone associated with a service by analyzing one or more electronic communications using natural language processing; determining, by the processor set, an impact urgency score based on the service availability impact and the user tone; determining, by the processor set, a scale-by value based on the impact urgency score; and scaling, by the processor set and based on the scale-by value, a computing cluster running a workload that provides the service. the method may include: creating a story that includes information defining the service, the impact urgency score, the scale-by value, and a date and time the scaling was performed; saving the story in a repository; identifying a pattern by analyzing plural stories saved in the repository as a time series; and proactively scaling the computing cluster running the workload based on the identified pattern.
Inventor(s): Humberto Orozco Cervantes of Tonalá (MX) for international business machines corporation, Paul Llamas Virgen of Guadalajara (MX) for international business machines corporation, Romelia H. Flores of Keller TX (US) for international business machines corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/08
Abstract: a method for authenticating a user to access a resource is disclosed. in one embodiment, such a method includes determining multiple devices on which to perform a multi-factor authentication sequence. the multiple devices include at least one virtual device and at least one physical device. as part of completing the multi-factor authentication sequence, the method requires a user to perform a first authentication action on a virtual device and a second authentication action on a physical device. in certain embodiments, the first authentication action and the second authentication action must be performed in a designated order and/or with a designated timing to successfully complete the multi-factor authentication sequence. in response to the user completing the multi-factor authorization sequence on both the virtual device and the physical device, the method grants authorization to the user to access a resource. a corresponding system and computer program product are also disclosed.
Inventor(s): Juan Pablo Parga Jimenez of Guadalajara (MX) for international business machines corporation, Humberto Orozco Cervantes of Tonalá (MX) for international business machines corporation, Jose Ramon Navarro Marquez of Zapopan (MX) for international business machines corporation
IPC Code(s): H04L9/40, G06N7/08, H04L41/16
CPC Code(s): H04L63/145
Abstract: in one general embodiment, a computer-implemented method includes applying a plurality of known cyber-attack techniques and variations thereof against a simulated defender system using a simulated attacking system. known cyber-attack defense techniques are applied to the defender system. instances of the defender system are logged in association with various combinations of respective cyber-attack techniques, various cyber-attack defense techniques, simulated system configurations, and simulated system outcomes as training instances. a machine learning model is trained using the logged training instances. a production product configuration is input to the trained machine learning model. information related to cyber-hardening of the production product is output from the trained machine learning model.
Inventor(s): Clement Decrop of Arlington VA (US) for international business machines corporation, Olivia Monroe of Washington DC (US) for international business machines corporation, Daniel Austin Harting of Chesapeake Beach MD (US) for international business machines corporation, Benjamin Joseph DeLeo of Arlington VA (US) for international business machines corporation, Justin Wu of Rockville MD (US) for international business machines corporation
IPC Code(s): H04N21/25, H04N21/233, H04N21/234, H04N21/258, H04N21/2668, H04N21/81
CPC Code(s): H04N21/252
Abstract: a computer-implemented method for generating personalized multimedia, is disclosed. the computer-implemented method includes determining one or more multimedia preferences associated with a user. the computer-implemented method further includes analyzing multimedia data to generate a personalized audio output based, at least in part, on the one or more multimedia preferences associated with the user. the computer-implemented method further includes modifying the multimedia data to include the generated personalized audio output using a generative adversarial network.
Inventor(s): Biswanath Senapati of Mechanicville NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Seiji Munetoh of Tokyo (JP) for international business machines corporation
IPC Code(s): H10B63/00
CPC Code(s): H10B63/80
Abstract: a semiconductor structure is provided that includes a resistive random access memory located on a surface of a bitline that is embedded in a shallow trench isolation structure. the structure can further include a source line that is present above the bitline or embedded in the shallow trench isolation structure.
Inventor(s): Mukta Ghate Farooq of HOPEWELL JCT NY (US) for international business machines corporation, Arvind Kumar of Chappaqua NY (US) for international business machines corporation
IPC Code(s): H10B80/00, H01L23/00, H01L23/48, H01L23/528, H01L23/538, H01L25/18
CPC Code(s): H10B80/00
Abstract: heterogeneous integration semiconductor packages with voltage regulation are described. a semiconductor device can include a chip including a memory device and a plurality of through-silicon-vias (tsvs). the semiconductor device can further include a processor arranged on top of the chip. the processor can be configured to communicate with the memory device via a plurality of interconnects. the semiconductor device can further include at least one voltage regulator arranged on top of the chip. the at least one voltage regulator can be configured to regulate power being provided from the plurality of tsvs to the processor.
Inventor(s): Baleegh Abdo of Fishkill NY (US) for international business machines corporation, Jae-Woong Nah of Closter NJ (US) for international business machines corporation
IPC Code(s): H10N60/81, H10N60/01, H10N60/82, H10N69/00
CPC Code(s): H10N60/81
Abstract: a structure includes a first device having a first chip and a second chip. the second chip has a first side with a plurality of bumps and a second side with a plurality of first superconducting lines. a solder bonded layer attaches the first chip to the second chip. a second device has a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side opposite the first side having a plurality of second superconducting lines. a solder shield material surrounds the plurality of bumps and the plurality of pads, and the plurality of bumps on the second chip are bonded to the plurality of pads on the second device. the solder shield material is connected to the plurality of first superconducting lines of the first device and to the plurality of second superconducting lines of the second device.
Inventor(s): Ning Li of White Plains NY (US) for international business machines corporation, Andrew Herbert Simon of Fishkill NY (US) for international business machines corporation, Injo Ok of Albany NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Timothy Mathew Philip of Albany NY (US) for international business machines corporation, Kevin W. Brew of Niskayuna NY (US) for international business machines corporation, Jin Ping Han of Yorktown Heights NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation, Nicole Saulnier of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
CPC Code(s): H01L45/1253
Abstract: an electrical device includes a first electrode in series with a second electrode. a phase change memory (pcm) is in series with the second electrode. a variable electrical element is in series with the phase change memory.
International Business Machines Corporation patent applications on June 27th, 2024
- International Business Machines Corporation
- B25J9/16
- CPC B25J9/1671
- International business machines corporation
- B29C64/188
- B22F10/60
- B22F10/73
- B22F10/85
- B23K26/16
- B23K26/361
- B29C64/357
- B29C64/393
- B33Y10/00
- B33Y40/20
- B33Y50/02
- CPC B29C64/188
- B29C64/40
- B29C64/176
- B29C64/236
- B29C64/245
- B29C64/321
- B29C64/35
- B33Y30/00
- B65G47/90
- CPC B29C64/40
- G01R33/035
- G06N10/00
- G06N10/40
- H03F19/00
- H03K3/38
- H03K5/00
- H03K17/92
- H10N60/12
- CPC G01R33/0358
- G06F8/41
- G06F8/71
- G06F9/54
- CPC G06F8/433
- G06F8/61
- CPC G06F8/63
- G06F11/07
- CPC G06F11/0778
- G06F11/34
- CPC G06F11/079
- G06F11/36
- CPC G06F11/3664
- G06F12/0802
- G06F12/10
- CPC G06F12/0802
- G06F12/1009
- G06F12/0882
- G06F12/1027
- CPC G06F12/1009
- G06F17/16
- G06N3/063
- CPC G06F17/16
- G06F21/51
- CPC G06F21/51
- G06F21/55
- CPC G06F21/554
- G06F30/27
- CPC G06F30/27
- G06N3/042
- CPC G06N3/042
- G06N3/08
- G06N3/047
- CPC G06N3/08
- G06N3/092
- CPC G06N3/092
- G06N20/00
- CPC G06N20/00
- G06Q10/0631
- CPC G06Q10/06313
- G06Q40/03
- G06Q20/40
- CPC G06Q40/03
- G06Q50/30
- G06F18/22
- G06Q10/083
- G06Q10/0833
- G06Q10/087
- G06Q30/0601
- CPC G06Q50/30
- G06V10/762
- G06V10/75
- G06V10/778
- CPC G06V10/762
- G06V10/774
- G06F40/284
- G06V10/80
- G06V20/62
- CPC G06V10/774
- G09G5/10
- G06T19/00
- G06T19/20
- CPC G09G5/10
- H01L21/768
- H01L23/528
- H01L23/532
- CPC H01L21/76843
- H01L21/311
- CPC H01L21/76879
- H01L23/522
- H01L21/8234
- H01L27/06
- H01L29/06
- CPC H01L23/5223
- H01L25/065
- H01L23/00
- H01L23/538
- H01L25/00
- CPC H01L25/0655
- H01L27/092
- H01L23/50
- H01L29/08
- H01L29/66
- CPC H01L27/092
- H01L21/8238
- H01L29/417
- H01L29/78
- H01L21/822
- H01L23/535
- H01L29/423
- H01L29/775
- CPC H01L27/0922
- H01L27/118
- H03K17/693
- CPC H01L27/11807
- H01L29/10
- CPC H01L29/0665
- CPC H01L29/1054
- CPC H01L29/41758
- H01L29/40
- CPC H01L29/41766
- H04L41/08
- G06F40/279
- G06F40/30
- H04L41/0893
- CPC H04L41/0879
- H04L9/40
- CPC H04L63/08
- G06N7/08
- H04L41/16
- CPC H04L63/145
- H04N21/25
- H04N21/233
- H04N21/234
- H04N21/258
- H04N21/2668
- H04N21/81
- CPC H04N21/252
- H10B63/00
- CPC H10B63/80
- H10B80/00
- H01L23/48
- H01L25/18
- CPC H10B80/00
- H10N60/81
- H10N60/01
- H10N60/82
- H10N69/00
- CPC H10N60/81
- H10N70/00
- H10N70/20
- CPC H01L45/1253
