Intel corporation (20240211344). ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING simplified abstract

ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING

Organization Name

intel corporation

Inventor(s)

Kuljit S. Bains of Olympia WA (US)

Kjersten E. Criss of Portland OR (US)

Rajat Agarwal of Portland OR (US)

Omar Avelar Suarez of Zapopan (MX)

Subhankar Panda of Portland OR (US)

Theodros Yigzaw of Sherwood OR (US)

Rebecca Z. Loop of Portland OR (US)

John G. Holm of Beaverton OR (US)

Gaurav Porwal of Portland OR (US)

ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240211344 titled 'ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING

The memory subsystem described in the patent application includes error checking and scrubbing (ECS) logic that can adjust the rate of ECS operations based on error detection in the memory when in automatic ECS mode. The ECS logic can also indicate rows of memory that have been offlined by the host, skip these rows in ECS operation counts, and respond to requests or hints from the host for ECS operations. An internal address generator in the ECS logic can choose between generated addresses and hints provided by the host.

Key Features and Innovation:

• Memory subsystem with ECS logic for error checking and scrubbing on-device
• Adaptive ECS operations based on error detection in memory
• Indication of offlined memory rows and skipping them in ECS operation counts
• Ability to respond to host requests or hints for ECS operations
• Internal address generator to select between generated addresses and hints

Potential Applications: - Data centers - High-performance computing systems - Embedded systems - Industrial control systems

Problems Solved: - Efficient error checking and scrubbing in memory subsystems - Adaptive response to memory errors - Improved reliability and data integrity in memory operations

Benefits: - Enhanced error detection and correction capabilities - Increased reliability of memory subsystems - Reduced risk of data corruption due to memory errors

Commercial Applications: Title: Adaptive Memory Subsystem with Error Checking and Scrubbing Logic This technology can be utilized in various commercial applications such as data centers, high-performance computing systems, and industrial control systems to enhance memory reliability and data integrity. The adaptive ECS operations based on error detection provide improved error checking and scrubbing capabilities, making it a valuable solution for critical systems where data integrity is paramount.

Questions about the technology: 1. How does the ECS logic adapt the rate of operations based on error detection? 2. What are the potential implications of triggering a row hammer response for specific memory addresses?

Original Abstract Submitted

a memory subsystem with error checking and scrubbing (ecs) logic on-device on the memory can adapt the rate of ecs operations in response to detection of errors in the memory when the memory device is in automatic ecs mode. the ecs logic can include an indication of rows of memory that have been offlined by the host. the ecs logic can skip the offlined rows in ecs operation counts. the ecs logic can include requests or hints by the host to have ecs operations performed. an internal address generator of the ecs logic can select between generated addresses and the hints. the system can allow a memory controller to detect multibit errors (mbes) related to a specific address of the associated memory. when the detected mbes indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.