Nvidia corporation (20240211166). HIERARCHICAL NETWORK FOR STACKED MEMORY SYSTEM simplified abstract
Contents
HIERARCHICAL NETWORK FOR STACKED MEMORY SYSTEM
Organization Name
Inventor(s)
William James Dally of Incline Village NV (US)
Carl Thomas Gray of Apex NC (US)
Stephen W. Keckler of Austin TX (US)
James Michael O'connor of Austin TX (US)
HIERARCHICAL NETWORK FOR STACKED MEMORY SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240211166 titled 'HIERARCHICAL NETWORK FOR STACKED MEMORY SYSTEM
The abstract describes a hierarchical network that enables access for a stacked memory system with multiple memory dies and processing tiles.
- Memory dies include multiple memory tiles, directly coupled to processing tiles for local memory access.
- Hierarchical network provides access paths for processing tiles to access local memory blocks, memory tiles in different dies, and memory tiles in different devices.
- Improved memory bandwidth to floating-point operation ratio and reduced energy consumption for data transfer.
Potential Applications: This technology could be used in high-performance computing systems, data centers, and artificial intelligence applications where fast and efficient memory access is crucial.
Problems Solved: This innovation addresses the challenge of optimizing memory access in stacked memory systems, improving performance and energy efficiency.
Benefits: The technology offers increased memory bandwidth, reduced energy consumption, and enhanced overall system performance in memory-intensive applications.
Commercial Applications: This technology could be valuable for companies developing advanced computing systems, supercomputers, and AI platforms that require high-speed memory access.
Questions about the technology: 1. How does this hierarchical network improve memory access in stacked memory systems? 2. What are the potential implications of the improved memory bandwidth to floating-point operation ratio in real-world applications?
Original Abstract Submitted
a hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. the processor die includes multiple processing tiles that are stacked with the one or more memory die. the memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. the hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. the ratio of memory bandwidth (byte) to floating-point operation (b:f) may improve 50� for accessing the local memory block compared with conventional memory. additionally, the energy consumed to transfer each bit may be reduced by 10�.
