Samsung electronics co., ltd. (20240203969). STACKED-CHIP PACKAGES simplified abstract
Contents
STACKED-CHIP PACKAGES
Organization Name
Inventor(s)
STACKED-CHIP PACKAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240203969 titled 'STACKED-CHIP PACKAGES
The abstract describes a stacked-chip package consisting of a first chip and a second chip stacked on top of each other. The first chip includes a cell array region, a core circuit region with a core terminal, and a peripheral circuit region with multiple peripheral circuit terminals. The second chip includes a cell array region on top of the first chip, a core circuit region with a core terminal on top of the first core circuit region, and a through via on the first peripheral circuit region connected to at least one peripheral circuit terminal.
- The innovative concept involves stacking two chips with different regions and terminals on top of each other.
- The first chip contains a cell array, core circuit, and peripheral circuit regions, while the second chip has a cell array and core circuit region on top of the first chip.
- A through via on the first chip connects to at least one peripheral circuit terminal, enabling communication between the chips.
- This design allows for more compact and efficient integration of multiple functionalities in a single package.
- The through via enhances connectivity and data transfer between the chips, improving overall performance.
Potential Applications: - This technology can be used in various electronic devices requiring compact and efficient chip packaging. - It can be beneficial in mobile devices, IoT devices, and other compact electronics where space is limited.
Problems Solved: - Addresses the challenge of integrating multiple functionalities in a small package. - Improves connectivity and data transfer between stacked chips.
Benefits: - Compact design saves space and reduces overall footprint. - Enhanced connectivity improves performance and efficiency of electronic devices.
Commercial Applications: Title: Innovative Stacked-Chip Package for Compact Electronics This technology can be utilized in the development of smartphones, tablets, wearables, and other compact electronic devices. The compact design and improved connectivity can enhance the performance and user experience of these products, making them more competitive in the market.
Questions about Stacked-Chip Package: 1. How does the through via on the first chip improve connectivity between the stacked chips? 2. What are the potential advantages of integrating multiple functionalities in a single stacked-chip package?
Original Abstract Submitted
a stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. the first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. the second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.
