Samsung electronics co., ltd. (20240203945). SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF simplified abstract
Contents
SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF
Organization Name
Inventor(s)
Yeongkwon Ko of Hwaseong-si (KR)
Teakhoon Lee of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240203945 titled 'SEMICONDUCTOR PACKAGE INCLUDING MOLD LAYER AND MANUFACTURING METHOD THEREOF
The semiconductor package described in the patent application consists of multiple layers surrounding the base chip and two semiconductor chips, providing protection and structural integrity to the components.
- The package substrate holds the base chip, which in turn holds the first semiconductor chip, followed by the second semiconductor chip.
- An inner mold layer covers the upper surface of the base chip and the side surfaces of the first and second semiconductor chips.
- A first outer mold layer is positioned between the package substrate and the base chip, partially covering the side surface of the base chip.
- A second outer mold layer is placed on top of the first outer mold layer, covering a portion of the side surface of the inner mold layer.
- The first and second outer mold layers have different viscosities, contributing to the overall structural integrity of the package.
Potential Applications: - This technology can be used in various electronic devices such as smartphones, tablets, and computers. - It can also be applied in automotive electronics, industrial equipment, and medical devices.
Problems Solved: - Provides protection and structural support to delicate semiconductor components. - Ensures the longevity and reliability of electronic devices by safeguarding the internal chips.
Benefits: - Enhanced durability and reliability of electronic devices. - Improved performance and longevity of semiconductor components. - Cost-effective solution for packaging semiconductor chips.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Device Reliability This technology can be utilized by semiconductor manufacturers to improve the quality and durability of their electronic products, leading to increased customer satisfaction and brand loyalty. It can also open up opportunities for partnerships with electronic device manufacturers looking to enhance the performance and longevity of their products.
Questions about Semiconductor Packaging Technology: 1. How does the different viscosities of the outer mold layers contribute to the overall structural integrity of the semiconductor package? - The different viscosities of the outer mold layers help in providing varying levels of support and protection to the semiconductor components, ensuring a balanced and robust structure.
2. What are the key factors to consider when designing a semiconductor package for optimal performance and reliability? - Factors such as material selection, layer thickness, and overall design layout play a crucial role in ensuring the effectiveness and longevity of the semiconductor package.
Original Abstract Submitted
a semiconductor package includes a package substrate on which a base chip is disposed. a first semiconductor chip is disposed on the base chip. a second semiconductor chip is disposed on the first semiconductor chip. an inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. a first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. a second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. the second outer mold layer is spaced apart from the package substrate. the first outer mold layer and the second outer mold layer have different viscosities.
