Samsung electronics co., ltd. (20240203850). SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Minjun Bae of Hwaseong-si (KR)
Gwangjae Jeon of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240203850 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
The semiconductor package described in the patent application consists of a redistribution substrate, a semiconductor chip on the top surface of the redistribution substrate, and a solder terminal on the bottom surface of the redistribution substrate. The redistribution substrate includes various patterns such as an under-bump pattern, a dielectric layer, an under-bump seed pattern, and a redistribution pattern.
- The under-bump pattern has central and edge regions, with the edge region having a higher top surface level than the central region.
- The angle between the bottom surface and the sidewall of the under-bump pattern falls within a range of 110° to 140°.
- The under-bump pattern is in contact with the solder terminal and plays a crucial role in the overall structure of the semiconductor package.
Potential Applications: - This technology can be used in various electronic devices that require efficient semiconductor packaging. - It can be applied in industries such as telecommunications, consumer electronics, and automotive electronics.
Problems Solved: - Provides a reliable and efficient method for fabricating semiconductor packages. - Ensures proper contact between the semiconductor chip and the solder terminal.
Benefits: - Improved performance and reliability of semiconductor packages. - Enhanced thermal management due to the optimized design of the under-bump pattern.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Performance This technology can be utilized in the production of high-performance electronic devices, catering to a wide range of industries. The market implications include increased efficiency and reliability of electronic products, leading to higher customer satisfaction and potentially greater market share for companies implementing this technology.
Questions about Semiconductor Packaging Technology: 1. How does the under-bump pattern contribute to the overall performance of the semiconductor package? 2. What are the key advantages of using this advanced semiconductor packaging technology in comparison to traditional methods?
Original Abstract Submitted
disclosed are semiconductor packages and their fabricating methods. the semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. the redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. the under-bump pattern has central and edge regions. a first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. an angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110� to 140�.
