Intel corporation (20240201949). SPARSITY-AWARE PERFORMANCE BOOST IN COMPUTE-IN-MEMORY CORES FOR DEEP NEURAL NETWORK ACCELERATION simplified abstract
Contents
SPARSITY-AWARE PERFORMANCE BOOST IN COMPUTE-IN-MEMORY CORES FOR DEEP NEURAL NETWORK ACCELERATION
Organization Name
Inventor(s)
Sagar Varma Sayyaparaju of Telangana (IN)
Sreenivas Subramoney of Bangalore (IN)
SPARSITY-AWARE PERFORMANCE BOOST IN COMPUTE-IN-MEMORY CORES FOR DEEP NEURAL NETWORK ACCELERATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240201949 titled 'SPARSITY-AWARE PERFORMANCE BOOST IN COMPUTE-IN-MEMORY CORES FOR DEEP NEURAL NETWORK ACCELERATION
The technology described in this patent application involves a compute-in-memory (CIM) enabled memory array that can perform digital bit-serial multiply and accumulate (MAC) operations on multi-bit input data and weight data stored within the memory array. This is achieved through the use of an adder tree connected to the memory array, an accumulator linked to the adder tree, and an input bit selection stage that limits the selection of serial bits on the input data to non-zero values during the MAC operations.
- The technology utilizes a CIM enabled memory array for performing MAC operations.
- An adder tree is employed to process the data within the memory array.
- An accumulator is used to store the results of the MAC operations.
- The input bit selection stage ensures that only non-zero values are selected during the operations.
Potential Applications: - This technology could be applied in digital signal processing systems. - It may find use in artificial intelligence and machine learning applications. - It could enhance the performance of arithmetic operations in various computing systems.
Problems Solved: - Improves the efficiency of multiply and accumulate operations. - Reduces the need for data movement between memory and processing units. - Enhances the speed and accuracy of mathematical computations.
Benefits: - Faster processing of multi-bit data. - Reduced power consumption due to in-memory computing. - Improved overall performance of computing systems.
Commercial Applications: Title: Enhanced Arithmetic Processing Technology for Advanced Computing Systems This technology could be utilized in high-performance computing systems, data centers, and specialized hardware for AI and machine learning applications. It has the potential to improve the efficiency and speed of arithmetic operations in various industries, including finance, healthcare, and scientific research.
Prior Art: Readers interested in exploring prior art related to this technology may want to investigate research papers and patents in the fields of in-memory computing, arithmetic processing, and digital signal processing.
Frequently Updated Research: Researchers in the field of advanced computing systems and hardware design are continuously exploring new methods to enhance computational efficiency. Stay updated on the latest developments in in-memory computing and arithmetic processing technologies to understand the evolving landscape of high-performance computing.
Questions about the Technology: 1. How does the use of a CIM enabled memory array improve the efficiency of arithmetic operations? 2. What are the potential implications of this technology for the future of computing systems?
Original Abstract Submitted
systems, apparatuses and methods may provide for technology that includes a compute-in-memory (cim) enabled memory array to conduct digital bit-serial multiply and accumulate (mac) operations on multi-bit input data and weight data stored in the cim enabled memory array, an adder tree coupled to the cim enabled memory array, an accumulator coupled to the adder tree, and an input bit selection stage coupled to the cim enabled memory array, wherein the input bit selection stage restricts serial bit selection on the multi-bit input data to non-zero values during the digital mac operations.
