18584181. MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
Contents
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Abhijeet Ashok Chachad of Plano TX (US)
Timothy Anderson of University Park TX (US)
David Matthew Thompson of Dallas TX (US)
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 18584181 titled 'MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
The abstract describes a processor system with a processor core, lower level cache memory, and higher level cache memory connected by a bypass path.
- The processor core generates memory transactions.
- The lower level cache memory has a lower memory controller.
- The higher level cache memory has a higher memory controller with a memory pipeline.
- The higher memory controller determines if a memory transaction is a bypass write.
- If it is a bypass write, the controller checks if there is a transaction preventing passing in the memory pipeline.
- If no such transaction is found, the memory transaction is sent to the lower memory controller using the bypass path.
Potential Applications: - High-performance computing systems - Data centers - Embedded systems
Problems Solved: - Efficient memory transaction handling - Reduced latency in memory access
Benefits: - Improved overall system performance - Enhanced memory access speed - Optimal utilization of cache memory
Commercial Applications: Title: "Optimized Memory Transaction System for Enhanced Performance in Processor Systems" This technology can be utilized in high-end computing devices, servers, and networking equipment to boost processing speeds and overall system efficiency.
Questions about the technology: 1. How does the bypass path in the memory controller improve memory transaction handling? 2. What are the key advantages of having a higher level cache memory with a memory pipeline in a processor system?
Original Abstract Submitted
In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.
