18587407. SEMICONDUCTOR PACKAGE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18587407 titled 'SEMICONDUCTOR PACKAGE AND METHOD
Simplified Explanation: The patent application describes a device with an integrated circuit die encapsulated in molding compound, a through via adjacent to the die, and a redistribution structure over the die, compound, and via.
Key Features and Innovation:
- Device includes molding compound, integrated circuit die, through via, and redistribution structure.
- Redistribution structure electrically connects die and via.
- Structure includes dielectric layers, conductive vias, and non-planar interface between vias.
Potential Applications: This technology could be used in various electronic devices requiring efficient electrical connections within a compact space.
Problems Solved: This technology addresses the challenge of creating reliable and compact electrical connections in integrated circuit devices.
Benefits:
- Improved electrical connectivity in compact devices.
- Enhanced reliability of integrated circuit connections.
- Efficient use of space within electronic devices.
Commercial Applications: Potential commercial applications include semiconductor manufacturing, consumer electronics, telecommunications equipment, and automotive electronics.
Prior Art: Readers can explore prior art related to this technology in the field of semiconductor packaging, integrated circuit design, and microelectronics manufacturing.
Frequently Updated Research: Researchers are continually exploring advancements in semiconductor packaging techniques, integrated circuit design, and microelectronics manufacturing processes.
Questions about the Technology: 1. What are the specific advantages of using a redistribution structure in this device? 2. How does the non-planar interface between the conductive vias improve the performance of the device?
Original Abstract Submitted
In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.
