18386472. MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE
Organization Name
Inventor(s)
Daeseok Byeon of Suwon-si (KR)
MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18386472 titled 'MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE
Simplified Explanation: The patent application describes memory devices with an asymmetric page buffer array architecture, where the row decoder array and page buffer array overlap the memory cell array structure.
- The memory device includes multiple memory planes within the cell array structure.
- The row decoder array is buried in a region overlapping the word line step region and a partial region of the memory cell array.
- The page buffer array connects bit lines of the buried memory cell array region to a first page buffer array, while bit lines outside this region connect to a second page buffer array.
Key Features and Innovation:
- Asymmetric page buffer array architecture in memory devices.
- Overlapping row decoder and page buffer arrays with the memory cell array structure.
- Efficient connection of bit lines to page buffer arrays based on the buried memory cell array region.
Potential Applications: This technology can be applied in various memory devices such as solid-state drives, flash memory, and other storage systems.
Problems Solved:
- Efficient organization of memory cell arrays.
- Improved data access and transfer speeds.
- Enhanced memory device performance.
Benefits:
- Increased data processing efficiency.
- Faster read and write operations.
- Enhanced overall performance of memory devices.
Commercial Applications: Potential commercial uses include in consumer electronics, data centers, cloud computing, and other industries requiring high-speed data storage and retrieval systems.
Prior Art: Prior art related to this technology may include research on memory device architectures, page buffer arrays, and memory cell array structures.
Frequently Updated Research: Stay updated on advancements in memory device technology, semiconductor manufacturing processes, and storage system innovations.
Questions about Memory Devices with Asymmetric Page Buffer Array Architecture: 1. How does the asymmetric page buffer array architecture improve memory device performance? 2. What are the potential challenges in implementing this technology in mass-produced memory devices?
Original Abstract Submitted
Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.
