Samsung electronics co., ltd. (20240194265). MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE simplified abstract
Contents
MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE
Organization Name
Inventor(s)
Daeseok Byeon of Suwon-si (KR)
MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240194265 titled 'MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURE
Simplified Explanation: Memory devices with an asymmetric page buffer array architecture are described in the patent application. The memory device includes a memory cell array with multiple memory planes, along with a row decoder array and a page buffer array that vertically overlap the cell array structure.
Key Features and Innovation:
- Memory device with an asymmetric page buffer array architecture.
- Memory cell array with multiple memory planes.
- Row decoder array and page buffer array vertically overlapping the cell array structure.
- Row decoder array buried in a region vertically overlapping a word line step region of the cell array structure.
- Page buffer array connecting bit lines of a partial region of the memory cell array to first and second page buffer arrays.
Potential Applications: This technology could be used in various memory devices such as solid-state drives, mobile devices, and computer systems.
Problems Solved: This technology addresses the need for efficient memory access and data storage in electronic devices.
Benefits:
- Improved memory access speed.
- Enhanced data storage capacity.
- Efficient utilization of memory space.
Commercial Applications: The technology could be applied in the development of faster and more efficient memory devices for consumer electronics, data centers, and other computing applications.
Prior Art: Readers interested in prior art related to this technology could explore patents and research papers in the field of memory device architectures and semiconductor memory technologies.
Frequently Updated Research: Researchers are continually exploring advancements in memory device architectures to improve performance and efficiency.
Questions about Memory Devices with Asymmetric Page Buffer Array Architecture: 1. What are the potential challenges in implementing this asymmetric page buffer array architecture in memory devices? 2. How does this innovation compare to traditional memory device architectures in terms of performance and efficiency?
Original Abstract Submitted
memory devices having an asymmetric page buffer array architecture are provided. the memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. the row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. in the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.
