Micron technology, inc. (20240188299). THREE-DIMENSIONAL MEMORY ARRAY FORMATION TECHNIQUES simplified abstract

THREE-DIMENSIONAL MEMORY ARRAY FORMATION TECHNIQUES

Organization Name

micron technology, inc.

Inventor(s)

Christopher J. Larsen of Boise ID (US)

S M Istiaque Hossain of Boise ID (US)

David A. Daycock of Boise ID (US)

Kevin R. Gast of Boise ID (US)

George Matamis of Eagle ID (US)

Lingyu Kong of Singapore (SG)

Sok Han Wong of Singapore (SG)

Lhaang Chee Ooi of Singapore (SG)

Wenjie Li of Singapore (SG)

THREE-DIMENSIONAL MEMORY ARRAY FORMATION TECHNIQUES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240188299 titled 'THREE-DIMENSIONAL MEMORY ARRAY FORMATION TECHNIQUES

The patent application describes methods, systems, and devices for forming a three-dimensional memory array. The memory device includes a stack of materials over a substrate, with arrays of first and second pillars extending through the stack. Some first pillars may be excluded from certain columns, creating variations in the width of the dielectric material in the stack.

• Memory device with a stack of materials over a substrate
• Arrays of first and second pillars extending through the stack
• Exclusion of first pillars from certain columns
• Variation in width of dielectric material in the stack

Potential Applications: - Memory storage devices - Semiconductor manufacturing - Data processing systems

Problems Solved: - Efficient three-dimensional memory array formation - Enhanced memory device performance - Improved data storage capacity

Benefits: - Increased memory density - Faster data access speeds - Enhanced reliability of memory devices

Commercial Applications: Title: "Innovative Three-Dimensional Memory Array Technology for Enhanced Data Storage" This technology can be utilized in the development of high-performance memory devices for various industries, including consumer electronics, data centers, and telecommunications.

Prior Art: Research on three-dimensional memory arrays and semiconductor manufacturing techniques.

Frequently Updated Research: Ongoing studies on optimizing the design and fabrication processes of three-dimensional memory arrays for improved performance and reliability.

Questions about Three-Dimensional Memory Array Formation: 1. How does the exclusion of first pillars from certain columns impact the overall performance of the memory device? 2. What are the potential challenges in scaling up this technology for mass production?

Original Abstract Submitted

methods, systems, and devices for three-dimensional memory array formation techniques are described. a memory device may include a stack of materials over a substrate. the memory device may include an array of first pillars and an array of second pillars extending at least partially through the stack of materials. one or more first pillars may be excluded from one or more columns of pillars of the array first pillars. the memory device may include dielectric material in a slit extending at least partially through the stack of materials. based on the exclusion of the one or more first pillars, the slit may have a greater width at a first portion through the stack of materials than a second portion through the stack of materials. the dielectric material located in the slit may also have a greater width at the first portion than at the second portion.