Patent Applications by Intel Corporation on 21st August 2025

Intel Corporation: 21 patent applications

Intel Corporation has applied for patents in the areas of G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}, 2), G06F9/30038 ({using a mask}, 2), G06F9/30043 ({LOAD or STORE instructions; Clear instruction}, 2), G06F9/30145 ({Instruction analysis, e.g. decoding, instruction word fields}, 2), G06F11/0709 (Responding to the occurrence of a fault, e.g. fault tolerance, 2), G06N3/08 (Learning methods, 2), G06N3/063 (using electronic means, 2), H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS, 2), H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS, 2), H10D30/43 (Technology classification, 2)

Top Inventors:

Raanan Sade of Portland OR US (2 patents)
Simon Rubanovich of Haifa IL (2 patents)
Amit Gradstein of Binyamina IL (2 patents)
Zeev Sperber of Zichron Yackov IL (2 patents)
Alexander Heinecke of San Jose CA US (2 patents)
Robert Valentine of Kiryat Tivon IL (2 patents)
Mark J. Charney of Lexington MA US (2 patents)
Bret Toll of Hillsboro OR US (2 patents)
Jesus Corbal of King City OR US (2 patents)
Elmoustapha Ould-Ahmed-Vall of Gilbert AZ US (2 patents)

Patent Applications by Intel Corporation

20250264739. PHOTONIC DEVICES WITH POLARIZATION-BASED WAVELENGTH COMBINING

Abstract: Photonic devices, packages, and systems are disclosed. An example photonic device includes a first optical waveguide to support propagation of a first multi-wavelength optical signal, a second optical waveguide to support propagation of a second multi-wavelength optical signal, a third optical waveg...

20250264936. COMPENSATING FOR HIGH HEAD MOVEMENT IN HEAD-MOUNTED DISPLAYS

Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only th...

20250265081. SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier ...

20250265085. SYSTEMS AND METHODS TO LOAD A TILE REGISTER PAIR

Abstract: Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, resp...

20250265125. TECHNOLOGIES FOR LOAD BALANCING DATA PROCESSING

Abstract: Examples described herein relate to circuitry to select a first load balancer from among multiple load balancers to allocate a packet to a processor core among multiple processor cores of a processor and change from the first load balancer to select a second load balancer among the multiple load bal...

20250265136. CONFIGURABLE STALL INJECTION FOR INTERFACE ERROR CHECKING

Abstract: A system that includes determining whether an interface between sender and receiver devices is defective. For an interface between a sender device and a receiver device: a configured number of stalls can be injected in a communication from the sender device to the receiver device. Based on the count...

20250265143. DEFECT DETECTION BASED ON ACOUSTIC SIGNALS

Abstract: Examples described herein relate to circuitry to receive data associated with a device and indicate whether the device is potentially malfunctioning based on anomalous sounds in an operational server and based on an activity indicator of the server. In some examples, the device includes one or more ...

20250265182. METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO THROTTLE MEMORY BANDWIDTH FOR POWER MANAGEMENT

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to throttle memory bandwidth for power management. An example apparatus includes machine-readable instructions and at least one programmable circuit to be programmed by the machine-readable instructions. The at least one programm...

20250265363. UNIFYING INTERFACE FOR CLOUD CONTENT SHARING SERVICES

Abstract: Methods and systems that allow a user to see the people or groups who have access to files that are maintained by a plurality of cloud content sharing services. In particular, the user may see what specific party has access to each particular file or directory, regardless of multiple cloud content s...

20250265461. DYNAMIC QUANTIZATION OF NEURAL NETWORKS

Abstract: An apparatus for applying dynamic quantization of a neural network is described herein. The apparatus includes a scaling unit and a quantizing unit. The scaling unit is to calculate an initial desired scale factors of a plurality of inputs, weights and a bias and apply the input scale factor to a su...

20250265464. METHODS AND APPARATUS TO PERFORM MACHINE-LEARNING MODEL OPERATIONS ON SPARSE ACCELERATORS

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to perform machine-learning model operations on sparse accelerators. An example apparatus includes first circuitry, second circuitry to generate sparsity data based on an acceleration operation, and third circuitry to instruct one...

20250265762. ALLOCATION AND SYNCHRONIZATION OF MULTIPLE QUEUES BY A GRAPHICS PROCESSING UNIT

Abstract: A system that includes a graphics processing unit (GPU) comprising multiple processors and circuitry to: parse a first queue of the multiple queues; at an arbitration point in the first queue, select a second queue of the multiple queues to parse based on a priority level of the second queue and a h...

20250265772. OCCLUSION CULLING FOR DEPTH VALUES IN A DEPTH BUFFER

Abstract: A system that includes a graphics processing unit (GPU) to determine whether the second primitive is potentially occluded, fully occluded, or not occluded by the first primitive based on a comparison of the minimum depth value of the first primitive and the maximum depth value of the second primitiv...

20250266114. METHODS AND APPARATUS TO DELETE AND PREVENT RECOVERY OF DATA STORED IN A MEMORY ARRAY

Abstract: Methods and apparatus to delete and prevent recovery of data stored in a memory array are disclosed. An example apparatus includes machine readable instructions; and at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to: obtain an instructio...

20250266340. MICROELECTRONIC ASSEMBLIES WITH SEALED LINERS FOR GLASS CORES

Abstract: A microelectronic assembly according to an embodiment of the present disclosure may include a glass core having a first face and a second face opposite the first face, and a TGV in the glass core, the TGV extending from the first face towards the second face and including a conductive material. The ...

20250266345. METHODS AND APPARATUS TO REDUCE DISCOLORATION OF SOLDER RESISTS IN IMMERSION COOLING ENVIRONMENTS

Abstract: Systems, apparatus, articles of manufacture, and methods to reduce discoloration of solder resists in immersion cooling environments are disclosed. An example apparatus includes a substrate. The example apparatus further includes a solder resist layer on an exterior surface of the substrate. The sol...

20250266395. MULTI-DIE BRIDGE ASSEMBLIES AND METHODS FOR THREE-DIMENSIONAL PACKAGING

Abstract: Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bu...

20250267015. VIRTUAL MICROCONTROLLER FOR DEVICE AUTHENTICATION IN A CONFIDENTIAL COMPUTING ENVIRONMENT

Abstract: Embodiments are directed to a virtual microcontroller for device authentication in a confidential computing environment. An embodiment includes a processor to implement a service trust domain (TD) as a virtual microcontroller (VMC) trust domain (VMC-TD) for a device, where the VMC-TD is to support p...

20250267448. TEMPORARY UE CAPABILITY RESTRICTIONS FOR SIMULTANEOUS NETWORK CONNECTIONS

Abstract: A computer-readable storage medium stores instructions for execution by one or more processors of a UE to configure the UE for simultaneous connection with a 5G NR network and at least a second network, and to cause the UE to perform operations. The operations include encoding UE capability informat...

20250267886. INTEGRATED CIRCUIT STRUCTURES WITH VOID-FREE INTERNAL SPACERS

Abstract: Integrated circuit structures having void-free internal spacers, and methods of fabricating integrated circuit structures having void-free internal spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the...