Patent Applications by NVIDIA Corporation on 21st August 2025

NVIDIA Corporation: 18 patent applications

NVIDIA Corporation has applied for patents in the areas of G06N3/0495 (Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs, 3), G06F9/3867 ({using instruction pipelines}, 2), G06F21/602 ({Providing cryptographic facilities or services}, 2), G06F21/64 (Protecting data integrity, e.g. using checksums, certificates or signatures, 2), G06F40/284 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models, 2), G06V20/56 (IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING, 2), G01R31/31813 (MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits, 1), G06F13/4221 (Bus transfer protocol, e.g. handshake; Synchronisation, 1), G06F2213/0026 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models, 1), G06F3/0655 ({Replication mechanisms}, 1)

Top Inventors:

Polychronis Xekalakis of Portland OR US (2 patents)
David Hass of Cupertino CA US (2 patents)
Guillermo J. Rozas of Los Gatos CA US (2 patents)
Yusuf Cagatay Tekmen of Raleigh NC US (2 patents)
Nickolas Andrew Fortino of San Jose CA US (2 patents)
Ross Segelken of Portland OR US (2 patents)
Michael P. Cornaby of Hillsboro OR US (2 patents)
Nikhita Kunati of San Ramon CA US (2 patents)
Sean Benton Franey of Portland OR US (2 patents)
William James Dally of Incline Village NV US (2 patents)

Patent Applications by NVIDIA Corporation

20250264528. Test Data Transfer in Multi-Die Systems

Abstract: An integrated circuit package includes two or more discrete semiconductor dies coupled to a package substrate. The dies include a primary die and at least one secondary die. The primary die includes an external data transfer interface, a direct memory access (“DMA”) controller, a primary cross-die b...

20250265008. SIMULTANEOUS DISTRIBUTED AND NON-DISTRIBUTED ADDRESS MAPS AND ROUTING PROTOCOLS IN A COMPUTING SYSTEM

Abstract: Various embodiments include techniques for performing memory operations in a computing system. A processing unit in the computing system performs memory operations by accessing memory using two concurrent memory address maps (AMAPs). The processing unit access memory via a first fine-grain distribut...

20250265052. SOFTWARE COMPILATION USING GRAPHS

Abstract: Apparatuses, systems, and techniques of generate a software program based on graph nodes that indicating hardware library functions to be performed. In at least one embodiment, a complier generates a software program that performs hardware library functions based on a graph having graph nodes. In at...

20250265092. DYNAMIC RECONFIGURATION OF A MULTI-CORE PROCESSOR TO A UNIFIED CORE

Abstract: A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In resp...

20250265221. ASYNCHRONOUS ON-CHIP NETWORK

Abstract: An on-chip network (NoC) is a critical component of a GPU, CPU, network switch, or accelerator. The network nodes may be arranged in a two-dimensional array with each network node coupled to neighboring network nodes vertically and horizontally, with or without diagonal connections. Conventional rou...

20250265224. DYNAMIC RECONFIGURATION OF A UNIFIED CORE PROCESSOR TO A MULTI-CORE PROCESSOR

Abstract: A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. Response to a command to operate the IC with multiple cores, the first pipeline is flushed. The first core is partitioned to obtain a second core ...

20250265306. MASKED REFERENCE SOLUTIONS FOR MATHEMATICAL REASONING USING LANGUAGE MODELS

Abstract: In various examples, a technique for performing a mathematical reasoning task includes inputting a first prompt that includes (i) a set of example mathematical problems, (ii) example masked solutions to the example mathematical problems, and (iii) a mathematical problem into a first machine learning...

20250265337. SECURE DEVICE ATTESTATION USING ENTITLEMENT TOKENS

Abstract: Apparatuses, systems, and techniques for issuing entitlement tokens to a root of trust allowing the root of trust to take certain action(s) with respect to a component that it secures, for example, to affect a change in the software and/or features available to the component it secures. In some embo...

20250265355. VISUAL AND AUDIO OUTPUT AUTHENTICATION IN AVATAR SYSTEMS

Abstract: A method for countering digital impersonation and unauthorized digital or audio usage due to a rise of deep-fake technologies is described. The method employs biometric authentication to ensure user authenticity in real-time during avatar or voice recording. Unique watermarks are generated at predet...

20250265422. TASK-ORIENTED ASSISTANT USING LANGUAGE MODELS

Abstract: Disclosed are systems and techniques that may generate task-oriented assistant responses to natural language requests of a user. The techniques include receiving a natural language request of a user and generating a task-oriented assistant response based on the natural language request. Generating t...

20250265453. TECHNIQUES FOR COMPRESSING A MACHINE-LEARNING MODEL

Abstract: Techniques for compressing a machine learning mode include executing a first trained machine learning model on training data to identify one or more activation tensors associated with at least one layer of the trained machine learning model; for each pairing of a first activation tensor included in ...

20250265454. TECHNIQUES FOR COMPRESSING A MACHINE-LEARNING MODEL

Abstract: Techniques for executing trained machine learning models comprise presenting input data as a first activation tensor to a first layer of a trained machine learning model, compressing the first activation tensor using a first projection matrix that corresponds to the first layer of the trained machin...

20250265467. TECHNIQUES FOR COMPRESSING ARTIFICIAL NEURAL NETWORKS

Abstract: At least one of the various embodiments is directed towards a computer-implemented method for generating trained artificial neural networks. The method includes, for each model layer included in a trained model, training one or more student model layers to mimic the model layer, for a first target d...

20250265472. DIFFUSION-REWARD ADVERSARIAL IMITATION LEARNING

Abstract: Imitation learning, or artificial intelligence-based learning from demonstration, aims to acquire an agent policy by observing and mimicking the behavior demonstrated in expert demonstrations. Imitation learning can be used to generate reliable and robust learned policies in a variety of tasks invol...

20250265846. LANDMARK MATCHING IN ENVIRONMENT RECONSTRUCTION SYSTEMS AND APPLICATIONS

Abstract: Approaches presented herein provide for the matching and alignment of features in different instances of sensor data captured for an environment. At least one embodiment provides for accurate identification of matching landmarks between two or more tracks obtained from sensor-equipped machines. Trac...

20250265847. SCALABLE SEMANTIC IMAGE RETRIEVAL WITH DEEP TEMPLATE MATCHING

Abstract: Approaches presented herein provide for semantic data matching, as may be useful for selecting data from a large unlabeled dataset to train a neural network. For an object detection use case, such a process can identify images within an unlabeled set even when an object of interest represents a rela...

20250265848. FEATURE IDENTIFICATION USING LANGUAGE MODELS FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

Abstract: In various examples, feature identification using language models for autonomous and semi-autonomous systems and applications is described herein. Systems and methods described herein may use a language model(s) to determine information associated with features, such as surface markings, within an e...

20250267108. ON-CHIP NETWORK WITH DIAGONAL CHANNELS

Abstract: An on-chip network (NoC) is a critical component of a GPU, CPU, network switch, or accelerator. NoC latency and energy is reduced by fabricating wires (conductive paths) on an integrated circuit die not only horizontally and vertically, but also diagonally between the network nodes. The diagonal wir...