NVIDIA Corporation patent applications on June 6th, 2024
Patent Applications by NVIDIA Corporation on June 6th, 2024
NVIDIA Corporation: 15 patent applications
NVIDIA Corporation has applied for patents in the areas of G06F40/56 (4), G06F40/284 (4), B60W60/00 (2), G06N3/08 (2), G06F40/279 (2)
With keywords such as: data, systems, based, generate, information, natural, test, generated, machine, and vehicle in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Yuxiao Chen of Newark CA (US) for nvidia corporation, Peter Karkus of Zurich (CH) for nvidia corporation, Boris Ivanovic of Mountain View CA (US) for nvidia corporation, Xinshuo Weng of North York (CA) for nvidia corporation, Marco Pavone of Stanford CA (US) for nvidia corporation
IPC Code(s): B60W60/00
Abstract: in various examples, policy planning using behavior models for autonomous and semi-autonomous systems and applications is described herein. systems and methods are disclosed that determine a policy for navigating a vehicle, such as a semi-autonomous vehicle or an autonomous vehicle (or other machine), where the policy allows for multistage reasoning that leverages future reactive behaviors of one or more other objects. for instance, a first behavior model (e.g., a trajectory tree) may be generated that represents candidate trajectories for the vehicle and one or more second behavior models (e.g., one or more scenario trees) may be generated that respectively represent future behaviors of the other object(s). the first behavior model and the second behavior model(s) may then be processed, such as in a closed-loop simulation based on a realistic data-driven traffic model, to determine the policy for navigating the vehicle.
Inventor(s): Jesse Hong of Edgewater NJ (US) for nvidia corporation, Urs Muller of Keyport NJ (US) for nvidia corporation, Bernhard Firner of Highland Park NJ (US) for nvidia corporation, Zongyi Yang of Eatontown NJ (US) for nvidia corporation, Joyjit Daw of New York NY (US) for nvidia corporation, David Nister of Bellevue WA (US) for nvidia corporation, Roberto Giuseppe Luca Valenti of Holmdel NJ (US) for nvidia corporation, Rotem Aviv of San Diego CA (US) for nvidia corporation
IPC Code(s): G01M17/007, B60W30/08, B60W30/12, B60W30/14, B60W50/00, B60W50/04, B60W60/00, G06F11/36, G06V10/774, G06V20/56, G07C5/08
Abstract: in various examples, sensor data recorded in the real-world may be leveraged to generate transformed, additional, sensor data to test one or more functions of a vehicle—such as a function of an aeb, cmw, ldw, alc, or acc system. sensor data recorded by the sensors may be augmented, transformed, or otherwise updated to represent sensor data corresponding to state information defined by a simulation test profile for testing the vehicle function(s). once a set of test data has been generated, the test data may be processed by a system of the vehicle to determine the efficacy of the system with respect to any number of test criteria. as a result, a test set including additional or alternative instances of sensor data may be generated from real-world recorded sensor data to test a vehicle in a variety of test scenarios.
Inventor(s): Tucker Ryer Hermans of Salt Lake City UT (US) for nvidia corporation, Jana Pavlasek of Ann Arbor MI (US) for nvidia corporation, Fabio Tozeto Ramos of Seattle WA (US) for nvidia corporation
IPC Code(s): G05D1/02, G05D1/00
Abstract: apparatuses, systems, and techniques to perform inference to determine a trajectory based at least in part on a loss function including a cost associated with an amount of divergence between a set of terminal states and a set of goal states within a goal region.
Inventor(s): Michael B. Sullivan of Austin TX (US) for nvidia corporation, Mohamed Tarek Bnziad Mohamed Hassan of Lowell MA (US) for nvidia corporation, Aamer Jaleel of Northborough MA (US) for nvidia corporation
IPC Code(s): G06F11/10
Abstract: implicit memory tagging (imt) mechanisms utilizing alias-free memory tags that enable hardware-assisted memory tagging without incurring storage overhead above those incurred by conventional tagging mechanisms, while providing enhanced data integrity and memory security. the imt mechanisms enhance the utility of error correcting codes (eccs) to test memory tags in addition to the traditional utility of eccs for detecting and correcting data errors and enable a finer granularity of memory tagging than many conventional approaches.
Inventor(s): Shubhadeep Das of Kolkata (IN) for nvidia corporation, Sumit Kumar Bhattacharya of Pune (IN) for nvidia corporation, Oluwatobi Olabiyi of Falls Church VA (US) for nvidia corporation
IPC Code(s): G06F16/332
Abstract: in various examples, hybrid models for determining intents in conversational ai systems and applications are disclosed. systems and methods are disclosed that use a machine learning model(s) and a data file(s) that associates requests (e.g., questions) with responses (e.g., answers) in order to generate final responses to requests. for instance, the machine learning model(s) may determine confidence scores that indicate similarities between the requests from the data file(s) and an input request represented by text data. the data file(s) is then used to determine, based on the confidence scores, one of the responses that is associated with one of the requests that is related to the input request. additionally, the response may then used to generate a final response to the input request.
Inventor(s): Benjamin Klenk of San Jose CA (US) for nvidia corporation, Al Davis of Coalville UT (US) for nvidia corporation, Larry Robert Dennison of Mendon MA (US) for nvidia corporation
IPC Code(s): G06F21/64
Abstract: messaging protocols used by components in a messaging system to exchange messages conventionally use a reliability mechanism to ensure that each message sent by a sender is received, without compromise, by the intended receiver. typically, this reliability mechanism involves use of a returned acknowledgement message to the message sender, with automatic retransmission of the message by the sender when the acknowledgement message is not received (e.g. within a defined timeframe). however, existing acknowledgement-based reliability mechanisms require that a sender identifier be included in the message header, which increases the overhead of the message. the present disclosure provides an epoch-based reliability mechanism that allows the sender identifier to be omitted from the message header to minimize overhead and maximize the efficient use of the available bandwidth.
Inventor(s): Ameya Sunil Mahabaleshwarkar of Pittsburgh PA (US) for nvidia corporation, Zhilin Wang of Seattle WA (US) for nvidia corporation, Oluwatobi Olabiyi of Falls Church VA (US) for nvidia corporation
IPC Code(s): G06F40/35, G06F16/2455, G06F40/279, G06F40/40
Abstract: in various examples, systems and methods are disclosed relating to generating dialogue responses from structured data for conversational artificial intelligence (ai) systems and applications. systems and methods are disclosed for training or updating a machine learning model—such as a deep neural network—for deployment using structured data from dialogues of multiple domains. the systems and methods can generate responses to users to provide a more natural user experience, such as by generating alternative outputs that vary in syntax with respect to how the outputs incorporate data used to respond to user utterances, while still accurately providing information to satisfy requests from users.
Inventor(s): Shubhadeep DAS of Kolkata (IN) for nvidia corporation, Yi-Hui LEE of Dallas TX (US) for nvidia corporation, Oluwatobi OLABIYI of Falls Church VA (US) for nvidia corporation, Zhilin WANG of Seattle WA (US) for nvidia corporation
IPC Code(s): G06F40/56, G06F40/284
Abstract: in various examples, a technique for slot filling includes receiving a natural language sentence from a user and identifying a first mention span included in the natural language sentence. the technique also includes determining, using a first machine learning model, that the first mention span is associated with a first slot class included in a set of slot classes based on a set of slot class descriptions corresponding to the set of slot classes.
20240185001.DATASET GENERATION USING LARGE LANGUAGE MODELS_simplified_abstract_(nvidia corporation)
Inventor(s): Divija Nagaraju of Mountain View CA (US) for nvidia corporation, Christopher Parisien of Toronto (CA) for nvidia corporation
IPC Code(s): G06F40/56, G06F40/284
Abstract: disclosed are systems and techniques that may generate datasets for training task-oriented dialogue systems. the techniques include generating natural language queries by selecting a template query, sampling one or more tokens from a data store of domain-specific tokens, modifying the selected template query using the one or more sampled tokens to generate a query prompt, and using a natural language generative machine-learning model to generate, based on the query prompt, a respective natural language query of the subset of the plurality of natural language queries, and causing the generated plurality of natural language queries to be provided to a machine-learning model training engine configured to train, using the generated plurality of natural language queries, a conversational machine-learning model to perform a domain-specific conversational task.
20240185034.GENERATING GLOBAL HIERARCHICAL SELF-ATTENTION_simplified_abstract_(nvidia corporation)
Inventor(s): Ali Hatamizadeh of Los Angeles CA (US) for nvidia corporation, Gregory Heinrich of Aix-en-Provence (FR) for nvidia corporation, Hongxu Yin of San Jose CA (US) for nvidia corporation, Jose Manuel Alvarez Lopez of Mountain View CA (US) for nvidia corporation, Jan Kautz of Lexington MA (US) for nvidia corporation, Pavlo Molchanov of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06N3/0455, G06N3/0464, G06N3/08
Abstract: apparatuses, systems, and techniques of using one or more machine learning processes (e.g., neural network(s)) to process data (e.g., using hierarchical self-attention). in at least one embodiment, image data is classified using hierarchical self-attention generated using carrier tokens that are associated with windowed subregions of the image data, and local attention generated using local tokens within the windowed subregions and the carrier tokens.
20240185100.PREPROCESSING DATA USING A NETWORK INTERFACE_simplified_abstract_(nvidia corporation)
Inventor(s): Alvin Ihsani of Everett MA (US) for nvidia corporation, Shaul Arazi of Tel-Aviv (IL) for nvidia corporation, Elena Agostini of Rome (IT) for nvidia corporation, Penn Tasinga of Bellevue WA (US) for nvidia corporation, Carl Everett Lacey, JR. of Palo Alto CA (US) for nvidia corporation, Dana Groff of Seattle WA (US) for nvidia corporation, Dotan David Levi of Kiryat Motzkin (IL) for nvidia corporation, Wojciech Wasko of Mtynek (PL) for nvidia corporation, Vishwesh Nath of Nashville TN (US) for nvidia corporation, Sachidanand Alle of Cambridge (GB) for nvidia corporation
IPC Code(s): G06N5/04, G16H30/20
Abstract: methods and systems for obtaining data having a first format, converting the data to a second format, storing the converted data in memory accessible by at least one parallel processing unit, and processing the converted data stored in the memory using the at least one parallel processing unit.
Inventor(s): Shinya MORINO of Tokyo (JP) for nvidia corporation
IPC Code(s): G06N10/20, G06N10/40
Abstract: aspects of this technical solution can identify, based at least on a representation of a quantum computing circuit, a first node of a topology of a computing platform configured to simulate at least a portion of the quantum computing circuit, compute a first metric indicating a first latency including the first node, the first latency based at least on a portion of the topology including the first node, select a second node of the topology having a second metric indicating a second latency less than the first latency, the second latency based at least on a portion of the topology including the second node, and simulate the quantum computing circuit on the computing platform using the second node.
20240185396.VISION TRANSFORMER FOR IMAGE GENERATION_simplified_abstract_(nvidia corporation)
Inventor(s): Ali Hatamizadeh of Los Angeles CA (US) for nvidia corporation, Jiaming Song of San Carlos CA (US) for nvidia corporation, Jan Kautz of Lexington MA (US) for nvidia corporation, Arash Vahdat of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06T5/00, G06T1/20, G06T7/00
Abstract: apparatuses, systems, and techniques to generate images. in at least one embodiment, one or more machine learning models generate an output image based, at least in part, on calculating attention scores using time embeddings.
Inventor(s): Wenzheng Chen of Toronto (CA) for nvidia corporation, Joey Litalien of Montreal (CA) for nvidia corporation, Jun Gao of North York (CA) for nvidia corporation, Zian Wang of Toronto (CA) for nvidia corporation, Clement Tse Tsian Christophe Louis Fuji Tsang of Toronto (CA) for nvidia corporation, Sameh Khamis of Oakland CA (US) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation
IPC Code(s): G06T15/06, G06T15/50, G06T19/20
Abstract: in various examples, information may be received for a 3d model, such as 3d geometry information, lighting information, and material information. a machine learning model may be trained to disentangle the 3d geometry information, the lighting information, and/or material information from input data to provide the information, which may be used to project geometry of the 3d model onto an image plane to generate a mapping between pixels and portions of the 3d model. rasterization may then use the mapping to determine which pixels are covered and in what manner, by the geometry. the mapping may also be used to compute radiance for points corresponding to the one or more 3d models using light transport simulation. disclosed approaches may be used in various applications, such as image editing, 3d model editing, synthetic data generation, and/or data set augmentation.
Inventor(s): Dongsu ZHANG of Seoul (KR) for nvidia corporation, Amlan KAR of Toronto (CA) for nvidia corporation, Francis WILLIAMS of Brooklyn NY (US) for nvidia corporation, Zan GOJCIC of Zurich (CH) for nvidia corporation, Karsten KREIS of Vancouver (CA) for nvidia corporation, Sanja FIDLER of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/10
Abstract: in various examples, a technique for performing three-dimensional (3d) scene completion includes determining an initial representation of a first 3d scene. the technique also includes executing a machine learning model to generate a first update to the initial representation at a previous time step and a second update to the initial representation at a current time step, wherein the second update is generated based at least on a threshold applied to a set of predictions corresponding to the first update. the technique also includes generating a 3d model of the 3d scene based at least on the second update to the initial representation.
- NVIDIA Corporation
- B60W60/00
- Nvidia corporation
- G01M17/007
- B60W30/08
- B60W30/12
- B60W30/14
- B60W50/00
- B60W50/04
- G06F11/36
- G06V10/774
- G06V20/56
- G07C5/08
- G05D1/02
- G05D1/00
- G06F11/10
- G06F16/332
- G06F21/64
- G06F40/35
- G06F16/2455
- G06F40/279
- G06F40/40
- G06F40/56
- G06F40/284
- G06N3/0455
- G06N3/0464
- G06N3/08
- G06N5/04
- G16H30/20
- G06N10/20
- G06N10/40
- G06T5/00
- G06T1/20
- G06T7/00
- G06T15/06
- G06T15/50
- G06T19/20
- G06T17/10
