Patent Applications by Micron Technology Inc on 24th July 2025

Micron Technology Inc: 36 patent applications

Micron Technology Inc has applied for patents in the areas of G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}, 8), G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}, 7), G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}, 4), G06F3/0653 ({Monitoring storage devices or systems}, 3), G11C16/0483 ({comprising cells having several storage transistors connected in series}, 3)

Patent Applications by Micron Technology Inc

20250237490. NON-CONTACT WAFER METROLOGY SYSTEM

Abstract: A capacitance sensing device including a semiconductor wafer having a frontside surface and a backside surface, a plurality of capacitance sensing units disposed close to the frontside surface of the semiconductor wafer, a plurality of first electrodes disposed on the backside surface of the semicon...

20250238133. RUNTIME STORAGE CAPACITY REDUCTION AVOIDANCE IN SEQUENTIALLY-WRITTEN MEMORY DEVICES

Abstract: A system includes a memory device including blocks. A first subset of the blocks is configured to store a first number of bits and a second subset of the blocks is configured to store a second number of bits, where the second number of bits is greater than the first number of bits. A processing devi...

20250238137. PROGRAMMING VIDEO DATA TO DIFFERENT PORTIONS OF MEMORY

Abstract: Programming video data to different portions of memory is described herein. An example system includes a host interface, a memory device having a first portion and a second portion, and a controller coupled to the host interface and the memory device. The controller can be configured to program vide...

20250238138. TECHNIQUES TO IMPROVE BOOT UP LATENCY OF A MEMORY SYSTEM

Abstract: Methods, systems, and devices for techniques to improve boot up latency of a memory system are described. As one example of the methods, a memory system may receive an indication to perform a power down operation and write, based on the indication, information corresponding to the power down operati...

20250238142. HOST TECHNIQUES FOR STACKED MEMORY SYSTEMS

Abstract: Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the s...

20250238144. HEADROOM MANAGEMENT DURING PARALLEL PLANE ACCESS IN A MULTI-PLANE MEMORY DEVICE

Abstract: A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to receive a request for one of the plurality of independent plane driver circuits to execute a high current event on a corr...

20250238154. MANAGING A MEMORY SUB-SYSTEM USING A CROSS-HATCH CURSOR

Abstract: One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata ...

20250238161. WRITE PADDING DATA TO MEMORY DEVICE USING ON-DEVICE COPY

Abstract: Various embodiments provide for writing padding data to a memory device, such as a NOT-AND-type memory device, using an on-memory-device copy operation, which can be used as part of a memory system. According to some embodiments, writing padding data to one or more target blocks of a memory device c...

20250238163. STORING DATA IN A HOST MEMORY BUFFER

Abstract: The disclosure configures a memory sub-system controller to store data in a host memory buffer. The controller accesses data that identifies a host memory buffer (HMB) portion of a temporary storage device that has been allocated to a memory sub-system by a host. The controller generates a virtual a...

20250238165. APPARATUSES AND METHODS FOR STAGGERED REFRESH OPERATIONS ACROSS MEMORY DEVICES OF A MODULE

Abstract: A memory module includes a number of memory devices which receive refresh commands. Each memory device determines if it is that device's turn in a sequence, for example by counting the refresh commands. When it is not a device's turn, it performs refresh operations at a first rate responsive to the ...

20250238166. TRUTH TABLE EXTENSION FOR STACKED MEMORY SYSTEMS

Abstract: Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an exte...

20250238168. Adaptive Command Completion Timers

Abstract: Exemplary methods, apparatuses, and systems include receiving a request to perform an operation in memory. A subdivision of the memory to which the request is directed is determined. A command completion time based upon a command type for the operation and which subdivision of the memory to which th...

20250238318. DOUBLE DEVICE DATA CORRECTION IN MEMORY DEVICES USING ENLARGED REED-SOLOMON CODEWORDS

Abstract: In some implementations, a memory device may associate a first memory stripe with a second memory stripe. The memory device may receive a first codeword associated with the first memory stripe. The memory device may identify, using the first codeword, a first error in a first set of data bits that a...

20250238321. CRYPTOGRAPHIC DATA INTEGRITY PROTECTION

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a fir...

20250238327. RECOVERY MODE FOR MEMORY DEVICE

Abstract: Implementations described herein relate to implementing a recovery mode for a memory device. In some implementations, the memory device may include memory and one or more components. The one or more components may be configured to receive, from a host system, an indication that the memory device is ...