18354246. STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES simplified abstract (SanDisk Technologies LLC)
Contents
- 1 STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES
Organization Name
Inventor(s)
Akihiro Tobioka of Nagoya (JP)
Takayuki Maekura of Yokkaichi (JP)
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18354246 titled 'STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES
Simplified Explanation
The patent application describes a method for forming memory opening fill structures in a semiconductor device by alternating insulating layers and sacrificial material layers, replacing the sacrificial material layers with electrically conductive layers, and providing electrical contacts to the electrically conductive layers.
- Memory opening fill structures are formed by stacking memory elements in memory openings.
- Sacrificial material layers are replaced with electrically conductive layers.
- Electrical contacts to the electrically conductive layers are provided through integrated layer-and-via structures or integrated line-and-via structures.
Potential Applications
The technology described in the patent application could be applied in the semiconductor industry for the manufacturing of memory devices, such as DRAM or NAND flash memory.
Problems Solved
This technology solves the problem of efficiently forming memory opening fill structures with electrically conductive layers in a semiconductor device.
Benefits
The benefits of this technology include improved performance and reliability of memory devices, as well as potentially reducing manufacturing costs.
Potential Commercial Applications
"Enhancing Memory Device Performance with Integrated Layer-and-Via Structures"
Possible Prior Art
There may be prior art related to the formation of memory opening fill structures in semiconductor devices, but specific examples are not provided in the patent application.
What materials are used for the insulating layers and sacrificial material layers in this process?
The patent application does not specify the exact materials used for the insulating layers and sacrificial material layers. Further research or examination of the full patent document may provide more details on the materials utilized in this process.
How does the integration of line-and-via structures improve the efficiency of providing electrical contacts in the semiconductor device?
The patent application briefly mentions the use of integrated line-and-via structures for providing electrical contacts to the electrically conductive layers. A more in-depth analysis or study of the patent document could reveal the specific advantages and efficiencies gained from this integration in the semiconductor device manufacturing process.
Original Abstract Submitted
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, memory openings are formed through the alternating stack, and memory opening fill structures including a respective vertical stack of memory elements are formed in the memory openings. The sacrificial material layers are replaced with electrically conductive layers. Electrical contacts to the electrically conductive layers may be provided by forming integrated layer-and-via structures that simultaneously forms metallic via portions as an integral portion of a continuous electrically conductive structure that includes a respective electrically conductive layer. Alternatively, electrical contacts to the electrically conductive layers may be provided by forming integrated line-and-via structures that includes a metallic plate portion contacting a respective electrically conductive layer and a metallic via portion.
