18349578. STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS simplified abstract (SanDisk Technologies LLC)
Contents
- 1 STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS
Organization Name
Inventor(s)
Takayuki Maekura of Yokkaichi (JP)
Takaaki Iwai of Yokkaichi (JP)
Keisuke Izumi of Yokkaichi (JP)
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18349578 titled 'STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS
Simplified Explanation
The memory device described in the patent application consists of an alternating stack of insulating layers and composite layers, with memory openings extending vertically through the stack. Memory opening fill structures are located in the memory openings, each containing memory elements, a semiconductor channel, and integrated line-and-via structures. These line-and-via structures include a conductive plate portion that contacts the electrically conductive layer of the composite layers, and a conductive via portion that extends vertically through the insulating layers and dielectric material plates.
- Memory device with alternating insulating and composite layers
- Memory openings with fill structures containing memory elements and integrated line-and-via structures
- Line-and-via structures connecting memory elements to electrically conductive layers
Potential Applications
The technology described in the patent application could be applied in:
- Data storage devices
- Semiconductor manufacturing
- Memory modules for electronic devices
Problems Solved
This technology addresses issues such as:
- Increasing memory density
- Improving data storage efficiency
- Enhancing semiconductor performance
Benefits
The benefits of this technology include:
- Higher memory capacity
- Faster data access speeds
- Improved overall device performance
Potential Commercial Applications
The potential commercial applications of this technology could include:
- Memory chip manufacturing
- Consumer electronics production
- Data center storage solutions
Possible Prior Art
One possible prior art for this technology could be the use of integrated line-and-via structures in memory devices to improve data storage efficiency and performance.
Unanswered Questions
How does this technology compare to existing memory devices in terms of speed and capacity?
This article does not provide a direct comparison between this technology and existing memory devices in terms of speed and capacity. Further research or testing would be needed to determine the performance differences.
What are the potential challenges in implementing this technology on a large scale for commercial production?
This article does not address the potential challenges in implementing this technology on a large scale for commercial production. Factors such as cost, scalability, and compatibility with existing manufacturing processes would need to be considered.
Original Abstract Submitted
A memory device includes an alternating stack of insulating layers and composite layers, where each of the composite layers contains an electrically conductive layer and a dielectric material plate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel and a plurality of integrated line-and-via structures. Each of the plurality of integrated line-and-via structures includes a conductive plate portion that contacts the electrically conductive layer of a respective one of the composite layers, and a conductive via portion that is adjoined to a top surface of the conductive plate portion and vertically extends through a respective overlying subset of the insulating layers and a subset of the dielectric material plates of the composite layers.
