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20250217295. Partitioning And/or Gradual (Intel)

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PARTITIONING AND/OR GRADUAL RE-KEYING OF RANDOMIZED CACHES

Abstract: techniques for partitioning and/or gradual re-keying of randomized caches are described. in certain examples, an apparatus includes an execution circuit to cause a memory access request; a cache to store a plurality of sets, each of the sets to include a plurality of cache lines; and a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request by encrypting a first subset of bits of the address of the memory access request to generate an encrypted value, and generating the randomized index based on a first subset of bits of the encrypted value. the encrypting is to be based on a first key for a first segment of the cache and a second segment of the cache during a first period, on a second key for the first segment of the cache and the first key for the second segment of the cache during a second period, and on the second key for the first segment of the cache and the second segment of the cache during a third period.

Inventor(s): Thomas Unterluggauer, Fangfei Liu, Scott D. Constable, Carlos V. Rozas, Gilles Pokam, Boris Dolgunov

CPC Classification: G06F12/0877 (Cache access modes)

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