APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR MATRIX TRANSPOSE

Abstract: examples detailed herein at least include transpose circuitry that is external to a matrix operations accelerator. in some examples, the transpose circuitry at least includes a plurality of transpose engines to transpose a source matrix operand of a single instruction to generate a transposed source matrix, and control circuitry to direct the plurality of transpose engines to alternately operate in a parallel loading mode and a serial loading mode to generate the transposed source matrix, wherein the plurality of transposes engines and the control circuitry are at least a portion of transpose circuitry.

Inventor(s): Kamlesh PILLAI, Christopher J. HUGHES, Vinay JOSHI, Om Ji OMER

CPC Classification: G06F9/30181 ({Instruction operation extension or modification})

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