17793145. MICRO SEMICONDUCTOR CHIP TRANSFER SUBSTRATE, DISPLAY TRANSFERRING STRUCTURE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE DISPLAY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)

MICRO SEMICONDUCTOR CHIP TRANSFER SUBSTRATE, DISPLAY TRANSFERRING STRUCTURE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE DISPLAY DEVICE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Junsik Hwang of Hwaseong-si (KR)

Seogwoo Hong of Yongin-si (KR)

Kyungwook Hwang of Seoul (KR)

Hyunjoon Kim of Seoul (KR)

Joonyong Park of Suwon-si (KR)

MICRO SEMICONDUCTOR CHIP TRANSFER SUBSTRATE, DISPLAY TRANSFERRING STRUCTURE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE DISPLAY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17793145 titled 'MICRO SEMICONDUCTOR CHIP TRANSFER SUBSTRATE, DISPLAY TRANSFERRING STRUCTURE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE DISPLAY DEVICE

Simplified Explanation

The micro semiconductor chip transferring substrate described in the abstract includes a mold with recesses and a surface energy reduction pattern to improve alignment during wet alignment methods.

• Mold with recesses formed in a certain depth from the upper surface
• Surface energy reduction pattern with uneven patterns between recesses
• Improves sliding of micro semiconductor chips towards the recesses during alignment

Potential Applications

This technology could be applied in semiconductor manufacturing processes where precise alignment of microchips is crucial.

Problems Solved

This innovation solves the issue of chips sliding out of alignment during wet alignment methods, improving the overall efficiency of the process.

Benefits

The surface energy reduction pattern helps to ensure accurate alignment of micro semiconductor chips, leading to higher quality and more reliable electronic devices.

Potential Commercial Applications

This technology could be utilized in the production of various electronic devices such as smartphones, computers, and other consumer electronics.

Possible Prior Art

There may be prior art related to surface energy reduction patterns in semiconductor manufacturing processes, but specific examples are not provided in this context.

How does the surface energy reduction pattern affect the overall yield of the semiconductor manufacturing process?

The abstract does not mention the impact of the surface energy reduction pattern on the yield of the manufacturing process. It would be interesting to know if this technology leads to a higher yield of functional chips.

Are there any limitations to the use of this micro semiconductor chip transferring substrate in certain manufacturing environments?

It is not clear from the abstract if there are any limitations or specific conditions under which this technology may not be as effective. Understanding any potential limitations could help in assessing the broader applicability of this innovation.

Original Abstract Submitted

According to an aspect of an embodiment, provided is a micro semiconductor chip transferring substrate including: a mold including a plurality of recesses formed to be recessed in a certain depth from an upper surface; and a surface energy reduction pattern formed in region between the plurality of recesses, on the upper surface, the surface energy reduction pattern including a plurality of uneven patterns. When the micro semiconductor chips are aligned by a wet alignment method, by such surface energy reduction pattern, sliding of the micro semiconductor chips toward the inside of the recesses may be improved.