18226352. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyung Don Mun of Suwon-si (KR)
Kyoung Lim Suk of Suwon-si (KR)
Shang-Hoon Seo of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18226352 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a unique connection structure with a conductive pattern that vertically penetrates the connection substrate, allowing for a more compact design with improved electrical connections.
- The semiconductor package includes a first redistribution substrate, a semiconductor chip, a connection structure, a second redistribution substrate, and a molding layer.
- The connection structure consists of a connection substrate and a post, with the post in contact with the conductive pattern on the connection substrate.
- The width of the post is less than the width of the connection substrate, allowing for a more space-efficient design.
Potential Applications
This technology could be applied in various electronic devices such as smartphones, tablets, and laptops to improve the performance and reliability of semiconductor packages.
Problems Solved
This innovation solves the problem of limited space in semiconductor packages by providing a compact design with efficient electrical connections.
Benefits
The benefits of this technology include improved electrical connections, space efficiency, and enhanced performance in electronic devices.
Potential Commercial Applications
The technology could be utilized by semiconductor manufacturers to produce advanced semiconductor packages for consumer electronics, automotive applications, and industrial equipment.
Possible Prior Art
One possible prior art could be the use of vertical interconnects in semiconductor packages to improve electrical connections and space efficiency.
Unanswered Questions
How does this technology compare to existing semiconductor packaging solutions in terms of cost-effectiveness?
The article does not provide information on the cost-effectiveness of this technology compared to other semiconductor packaging solutions.
What impact could this technology have on the overall size and weight of electronic devices?
The article does not address the potential impact of this technology on the size and weight of electronic devices where it could be implemented.
Original Abstract Submitted
A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.
