18334790. SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF simplified abstract (Samsung Electronics Co., Ltd.)
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SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF
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SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18334790 titled 'SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF
Simplified Explanation
The operating method of a self-selecting memory device involves applying write pulses of opposite polarities to different memory cells with varying pulse widths.
- Write pulses with opposite polarities are applied to different memory cells.
- The first pulse width is longer than the second pulse width.
- Potential Applications:**
This technology could be applied in:
- Non-volatile memory devices
- Data storage systems
- Embedded systems
- Problems Solved:**
This technology helps in:
- Improving memory cell performance
- Enhancing data storage efficiency
- Increasing memory device reliability
- Benefits:**
The benefits of this technology include:
- Faster data writing speeds
- Higher memory density
- Lower power consumption
- Potential Commercial Applications:**
The potential commercial applications of this technology could be in:
- Solid-state drives (SSDs)
- Smartphones and tablets
- Internet of Things (IoT) devices
- Possible Prior Art:**
One possible prior art could be the use of multi-level cell (MLC) technology in memory devices to store multiple bits per cell.
- Unanswered Questions:**
1. How does the varying pulse widths affect the overall performance of the memory device? 2. Are there any limitations to the number of states that can be reliably stored using this method?
Original Abstract Submitted
An operating method of a self-selecting memory device, includes an operation of applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width, and an operation of applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width, wherein the first write pulse and the second write pulse have substantially opposite polarities, wherein the first pulse width is longer than the second pulse width.
