Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on May 30th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on May 30th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 48 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (14), H01L21/56 (13), H01L27/092 (10), H01L21/02 (10), H01L23/00 (9)
With keywords such as: layer, structure, semiconductor, device, conductive, dielectric, gate, portion, substrate, and formed in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Hung-Chih Ou of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Fu Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hao Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Keh-Jeng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ho Chang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F119/18
Abstract: a method of process technology assessment is provided. the method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (eda) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
Inventor(s): Ching Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Yao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lin Chuang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/392, G06N5/04, G06N20/00
Abstract: a method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (drc) violations of a new electronic circuit placement layout; identifying hard-to-fix (htf) drc violations among the drc violations based on the fix rates of the drc violations of the new electronic circuit placement layout; and fixing, by an engineering change order (eco) tool, the drc violations.
Inventor(s): Win-San KHWA of Taipei city (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Jen WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Chieh LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16
Abstract: a circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. the first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. the second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. the feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.
Inventor(s): Hsuan-Ying MAI of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chun LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B08B1/12, B08B3/04, H01L21/67
Abstract: in accordance with some embodiments, a method includes placing a semiconductor wafer over a wafer stage; pressing a brush assembly against a backside surface of the semiconductor wafer, wherein the brush assembly comprises an inner brush member and an outer brush member laterally surrounding the inner brush member, and the outer brush member is made of a material having a lower rigidity than the inner brush member; rotating the brush assembly relative to the semiconductor wafer.
Inventor(s): Chun-Ming Lung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., ChunYao Wang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/02, H01L21/302, H01L21/3065, H01L21/308, H01L21/311, H01L21/3213, H01L21/8234
Abstract: a method includes depositing a hard mask over a target layer. depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. the method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun Chu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/3115, H01L27/092, H01L29/40, H01L29/423, H01L29/66
Abstract: a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/285, H01L21/8238, H01L27/092, H01L29/06, H01L29/40, H01L29/423, H01L29/786
Abstract: a device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. the gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.
Inventor(s): Yung-Sung Yen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Kuang Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Ching Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Shun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun Liu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng Gau of HsinChu City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Hsu Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, H01L21/033, H01L21/3213, H01L21/768, H01L21/8234, H01L21/8238
Abstract: a method includes forming a material layer over a substrate, forming a first hard mask (hm) layer over the material layer, forming a first trench, along a first direction, in the first hm layer. the method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first hm layer parallel to the first trench, by using the first spacers to guard the first trench. the method also includes etching the material layer through the first trench and the second trench, removing the first hm layer and the first spacers, forming a second hm layer over the material layer, forming a third trench in the second hm layer. the third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. the method also includes etching the material layer through the third trench.
Inventor(s): Chih-Piao CHUU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Yang LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lain-Jong LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/441, H01L21/02, H01L29/24, H01L29/66, H01L29/786
Abstract: a method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. the metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of s, se, te, and combinations thereof. a metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.
Inventor(s): Wei-Chun HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yen WANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chui-Ya PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/02
Abstract: in an embodiment, a method includes: immersing a wafer in a bath within a cleaning chamber, removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber, determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.
Inventor(s): Chien-Wei Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Ju Tsou of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/56, H01L21/683
Abstract: a manufacturing method of a semiconductor package includes the following steps. a semiconductor device is picked up from a carrier by a pick and place device, wherein the pick and place device includes a flexible head having a bonding portion configured to be in contact with the semiconductor device, a neck portion connecting the bonding portion, wherein a minimum width of the neck portion is substantially smaller than a maximum width of the bonding portion. the semiconductor device is placed and pressed onto a substrate by the pick and place device. an encapsulating material is formed over the substrate to laterally encapsulating the semiconductor device. a redistribution structure is formed over the semiconductor device and the encapsulating material. the substrate is removed.
Inventor(s): Wang-Chun HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Xuan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hou-Yu CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/764, H01L21/8234, H01L27/088, H01L29/06
Abstract: a semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. a top surface of the isolation feature is above a topmost surface of the first gate structure.
Inventor(s): Chia Cheng Chou of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chi Ko of Nantou (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532, H01L23/535
Abstract: a structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. the second conductive feature is over and contacting the first conductive feature. an air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. a protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.
Inventor(s): Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Chuan YOU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Lu LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/311, H01L21/3213, H01L27/088, H01L29/08, H01L29/40, H01L29/417, H01L29/66, H01L29/78
Abstract: semiconductor device structures and method for forming the same are provided. the semiconductor device structure includes a substrate and a gate stack formed over the substrate. the semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. in addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5�.
Inventor(s): Kuo-Cheng Ching of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Keung Leung of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/84, H01L27/092, H01L27/12, H01L29/66
Abstract: the present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. the method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
Inventor(s): Jen-Yuan CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L23/00, H01L23/48, H01L25/10
Abstract: a control circuit is included in a first die of a stacked semiconductor device. the first die further includes a transistor that is electrically connected to the control circuit. the transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. in this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. this may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.
Inventor(s): Che-Yu Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chia Chiu of Taoyan City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Wei Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Yu Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/24, H01L21/56, H01L23/00, H01L23/31, H01L25/00, H01L25/10, H01L25/16
Abstract: disclosed are a package, a package structure and a method of manufacturing a package structure. in one embodiment, the package includes a die, a plurality of through vias, at least one dummy structure, an encapsulant and a redistribution structure. the plurality of through vias surround the die. the at least one dummy structure is disposed between the die and the plurality of through vias and adjacent to at least one corner of the die. the encapsulant encapsulates the die, the plurality of through vias and the at least one dummy structure. the redistribution structure is disposed on the die, the plurality of through vias, the at least one dummy structure and the encapsulant and electrically connected to the die and the plurality of through vias.
20240178090.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chung-Ming Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Sung Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hung Tseng of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hsien Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L21/683, H01L23/48
Abstract: a package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. the semiconductor die is laterally encapsulated by an insulating encapsulation. the redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. the redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. the electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.
Inventor(s): Tzu-Sung Huang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Ming Hung Tseng of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Ming Tsai of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che Ho of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L21/768, H01L23/16, H01L23/522, H01L23/528
Abstract: in an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
Inventor(s): Wensen Hung of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Tsan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/373, H01L25/065, H10B80/00
Abstract: a semiconductor device includes a substrate, a first device, a second device, a ring structure, a lid structure, and a first adhesive layer. the first device is disposed on the substrate. the second device is adjacent to the first device and is disposed on the substrate. the ring structure is disposed over the substrate and the second device. the ring structure includes a cover and a leg extending out from the cover. the cover has a through opening. the lid structure is disposed over the ring structure and the first device. the lid structure includes a body and a protrusion protruding from the body. the protrusion of the lid structure is inserted into the through opening of the cover of the ring structure. the first adhesive layer is disposed between the body of the lid structure and the cover of the ring structure and includes phase change thermal interface material.
Inventor(s): Shih-Ting Hung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Wen Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L25/16
Abstract: a semiconductor package includes a redistribution structure and an encapsulated die electrically connected to the redistribution structure. the redistribution structure includes a first conductive pad, first and second conductive vias, and a first dielectric layer. the first conductive pad includes opposing first and second sides, the first conductive via lands on the first side of the first conductive pad and is tapered in a direction from the first side toward the second side. the second conductive via lands on the second side of the first conductive pad and is tapered in a direction from the second side toward the first side. the first dielectric layer laterally covers the first conductive pad and the first conductive via, and the first dielectric layer includes opposing first and second surfaces. the encapsulated die is disposed below the first side of the first conductive via.
Inventor(s): Chung-Ming Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Sung Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Kang Hsieh of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hung Tseng of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hsien Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chu-Chun Chueh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/544, H01L25/16
Abstract: an integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. the first redistribution structure has first regions and a second region surrounding the first regions. a metal density in the first regions is smaller than a metal density in the second region. the die is disposed over the first redistribution structure. the conductive structures are disposed on the first redistribution structure to surround the die. vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. the encapsulant encapsulates the die and the conductive structures. the second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
Inventor(s): Hong-Chih CHEN of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Yu-San CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih KAO of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/8234, H01L29/06, H01L29/417, H01L29/66, H01L29/786
Abstract: a semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. the structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. the structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.
Inventor(s): Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/285, H01L21/768, H01L21/8234, H01L23/528, H01L27/088, H01L29/417, H01L29/66, H01L29/78
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. the conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. the conductive structure also includes a first metal feature formed within the first concave recess. the semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hsien Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/311, H01L21/56, H01L23/00, H01L23/31, H01L25/00, H01L25/065, H01L25/10
Abstract: device, package structure and method of forming the same are disclosed. the device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. the conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. the dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.
Inventor(s): Wei-An LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, G06F30/31, G06F30/394, G06F30/398, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. an exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.
Inventor(s): Tzuan-Horng LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/56, H01L23/00, H01L25/16, H10B80/00
Abstract: a semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. the first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. the first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. the first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.
Inventor(s): Shih-Wei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yuan TENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chiahung LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., HAO-YI TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/544, H01L21/56, H01L23/31, H10B80/00
Abstract: the present disclosure relates to a method for forming a mark, a packaging method for a semiconductor device, and a semiconductor device having the mark, wherein the marking material is a polymer compound and the light transmittance of the marking material is less than 50%, which is suitable for forming the mark on the semiconductor device by laser sintering, and the marking material is sintered to make the resin cross-link and cure to form a cured product. in addition, in one embodiment, the cured product formed by the marking material can be used as a deflector to guide the flow of the underfill and control the flow rate of underfill, so as to effectively solve the problem of uneven flow rate of the underfill.
Inventor(s): Chien-Cheng CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Haw TSAO of Nan-Chu, Tai-chung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
Abstract: a chip structure is provided. the chip structure includes a substrate. the chip structure includes an interconnect layer over the substrate. the chip structure includes a conductive pad over the interconnect layer. the chip structure includes a conductive bump over the conductive pad. the conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, the first portion is between the neck portion and the conductive pad, and the neck portion is narrower than both of the first portion and the second portion. the chip structure includes a support layer over the second portion of the conductive bump. a first composition of the support layer is different from a second composition of the conductive bump. the chip structure includes a solder structure over the support layer.
Inventor(s): Ting-Yu Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hua Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyh Chwen Frank Lee of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56
Abstract: a structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. the redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. the metal pad is electrically disconnected from the power-ground macro.
Inventor(s): Wei-An LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8238, H01L23/522, H03K19/17736
Abstract: an integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. the backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. the horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. the backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer. one of the first terminal and the second terminal is a gate terminal of the first transistor while another one the first terminal and the second terminal is either a source terminal or a drain terminal of the first transistor.
Inventor(s): Xin-Yong WANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/768, H01L23/522
Abstract: an integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. the first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. the second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. the first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. the second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.
Inventor(s): Po-Lin PENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fu TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti SU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L23/60, H01L23/62, H01L27/06, H01L29/08, H01L29/10, H01L29/747, H01L29/861, H01L29/87
Abstract: a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. the second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the i/o pad and the first voltage terminal.
Inventor(s): Chung-Shu WU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Uei JANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yeh TANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An-Chyi WEI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/311, H01L21/768, H01L21/8234, H01L29/161
Abstract: a method for forming a finfet device structure is provided. the finfet device structure includes a first fin structure extending above a substrate, and a first liner layer formed on a first sidewall surface of the first fin structure. the finfet device structure includes a gate dielectric layer formed over the first fin structure and the first liner layer, wherein a sidewall surface of the gate dielectric layer is aligned with a sidewall surface of the first liner layer.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jer-Fu Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Iuliana Radu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L23/528, H01L29/06, H01L29/417, H01L29/423, H01L29/775
Abstract: a semiconductor device and a logic device formed of the semiconductor device are provided. the semiconductor device includes a first field effect transistor (fet), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second fet, disposed on the semiconductor substrate and overlapped with the first fet. a conductive type of the second fet is complementary to a conductive type of the first fet. second channel structures of the second fet are separately arranged along a lateral direction, and formed as thin walls.
Inventor(s): Ping-Yin Liu of Yonghe City (TW) for taiwan semiconductor manufacturing company, ltd., Yeur-Luen Tu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shiung Tsai of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Xiaomeng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Nan Tseng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
Abstract: a device includes two bsi image sensor elements and a third element. the third element is bonded in between the two bsi image sensor elements using element level stacking methods. each of the bsi image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. the substrate of the bsi image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. the third element also includes a substrate and a metal stack disposed over a first side of the substrate. the metal stacks of the two bsi image sensor elements and the third element are electrically coupled.
Inventor(s): Chun-Wei HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Hao HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Hsun CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L31/0232, H01L31/0236, H01L31/028, H01L31/0296, H01L31/0304, H01L31/032, H01L31/18
Abstract: an integrated circuit includes a photodetector. the photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. the photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. a dielectric layer covers the photosensitive material. the photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
Inventor(s): Feng-Ching Chu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L21/306, H01L21/3065, H01L29/08, H01L29/66, H01L29/78
Abstract: various examples of an integrated circuit device and a method for forming the device are disclosed herein. in an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. the device fin includes a channel region. a portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. the workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. a source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
Inventor(s): Chang-Yin CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Cheng CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/28, H01L29/66, H01L21/02, H01L21/027, H01L21/033, H01L21/3105, H01L21/311, H01L21/321, H01L21/762
Abstract: a device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. the multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. the inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. the outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. the dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.
Inventor(s): Yi-Ren CHEN of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ting LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/417, H01L29/423, H01L29/775
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. the device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.
Inventor(s): Harry-Hak-Lay Chuang of Singapore (SG) for taiwan semiconductor manufacturing company, ltd., Yi-Ren Chen of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Wen Liu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsiung Wang of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming Zhu of Singapore (SG) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L21/8238, H01L27/08, H01L27/092, H01L29/78
Abstract: the present disclosure provides one embodiment of a semiconductor structure. the semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (fet) formed on the semiconductor substrate. the fet includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
Inventor(s): Aryan AFZALIAN of Chastre (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/10, H01L29/66
Abstract: a method includes the following steps. a substrate is etched, forming a core structure protruding out of a plane of the substrate. shallow trench isolation (sti) features are formed on opposite sides of the core structure. the substrate and a lower portion of the core structure are doped to form a first source/drain region with a first doping concentration. a barrier layer is grown on an upper portion of the core structure. a first spacer is formed covering the sti features and covering the lower portion of core structure. a shell is formed wrapping the upper portion of the core structure and the barrier layer. the shell and the upper portion of the core structure have different doping conductivity types. a second source/drain region is formed with a second doping concentration over the shell. the first doping concentration and the second doping concentration are different from each other.
Inventor(s): Hsiang-Pi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Tien Tung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dawei Heh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., I-Ming Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Sheng Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzer-Min Shen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/40, H01L29/51, H01L29/66
Abstract: a semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. at least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. the first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. the third dopant species forms a plurality of second dipole elements having a second polarity. a first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.
Inventor(s): Wan-Yi Kao of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chi Ko of Nantou (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L29/66
Abstract: a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.
Inventor(s): Cheng-Hsien Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Lin Tseng of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Sheng Yu Lin of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chang Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Fang Tan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Fa Tu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chun Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/872, H01L21/762, H01L29/47
Abstract: embodiments include a schottky barrier diode (sbd) structure and method of forming the same, the sbd structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the sbd structure.
Inventor(s): Hsi-Sheng GOAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hsien HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K19/195, G06N10/40, H01L29/775
Abstract: a method is provided, including: applying a magnetic field according to a two-qubit gate operation performed with a quantum device; transmitting a voltage signal to a gate structure, arranged above first and second quantum dots in the quantum device, to generate a coupling signal that includes a first sine squared wave; and performing, by the magnetic field and the coupling signal, the two-qubit gate operation to the first and second qubits in the first and second quantum dots.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsin NIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
Abstract: an apparatus includes memory cells. a first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. the first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.
Inventor(s): Hengyuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, H01L23/528, H10N70/00
Abstract: a semiconductor device includes a first conductive layer, a memory layer, a second conductive layer and a selector layer. the memory layer surrounds the first conductive layer. the second conductive layer is disposed aside the memory layer. the selector layer is disposed on the second conductive layer. a first side of the second conductive layer is covered by the memory layer, a second side of the second conductive layer is covered by the selector layer, and a third side of the second conductive layer is exposed by the selector layer.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on May 30th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G06F30/398
- G06F119/18
- Taiwan semiconductor manufacturing company, ltd.
- G06F30/392
- G06N5/04
- G06N20/00
- G11C11/16
- H01L21/02
- B08B1/12
- B08B3/04
- H01L21/67
- H01L21/033
- H01L21/302
- H01L21/3065
- H01L21/308
- H01L21/311
- H01L21/3213
- H01L21/8234
- H01L21/28
- H01L21/3115
- H01L27/092
- H01L29/40
- H01L29/423
- H01L29/66
- H01L21/285
- H01L21/8238
- H01L29/06
- H01L29/786
- H01L21/768
- H01L21/441
- H01L29/24
- H01L21/56
- H01L21/683
- H01L21/762
- H01L21/764
- H01L27/088
- H01L23/532
- H01L23/535
- H01L29/08
- H01L29/417
- H01L29/78
- H01L21/84
- H01L27/12
- H01L21/66
- H01L23/00
- H01L23/48
- H01L25/10
- H01L23/24
- H01L23/31
- H01L25/00
- H01L25/16
- H01L23/16
- H01L23/522
- H01L23/528
- H01L23/367
- H01L23/373
- H01L25/065
- H10B80/00
- H01L23/498
- H01L21/48
- H01L23/544
- G06F30/31
- G06F30/394
- H01L23/538
- H01L27/02
- H03K19/17736
- H01L23/60
- H01L23/62
- H01L27/06
- H01L29/10
- H01L29/747
- H01L29/861
- H01L29/87
- H01L29/161
- H01L29/775
- H01L27/146
- H01L31/0232
- H01L31/0236
- H01L31/028
- H01L31/0296
- H01L31/0304
- H01L31/032
- H01L31/18
- H01L21/306
- H01L29/49
- H01L21/027
- H01L21/3105
- H01L21/321
- H01L27/08
- H01L29/51
- H01L29/872
- H01L29/47
- H03K19/195
- G06N10/40
- H10B10/00
- H10B63/00
- H10N70/00
