18513167. Asymmetric Stackup Structure for SoC Package Substrates simplified abstract (Apple Inc.)
Contents
- 1 Asymmetric Stackup Structure for SoC Package Substrates
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Asymmetric Stackup Structure for SoC Package Substrates - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Asymmetric Stackup Structure for SoC Package Substrates
Organization Name
Inventor(s)
Yikang Deng of San Jose CA (US)
Taegui Kim of San Jose CA (US)
Yifan Kao of Taoyuan City (TW)
Jun Chung Hsu of Cupertino CA (US)
Asymmetric Stackup Structure for SoC Package Substrates - A simplified explanation of the abstract
This abstract first appeared for US patent application 18513167 titled 'Asymmetric Stackup Structure for SoC Package Substrates
Simplified Explanation
The abstract describes an asymmetric stackup structure for an SoC package substrate, which includes a substrate with insulating material layers, a recess for an integrated passive device, build-up layers, and via paths connecting contacts.
- Substrate with insulating material layers
- Recess formed in upper surface of substrate for integrated passive device
- Build-up layers formed on top of substrate
- Via paths connecting contacts on lower surface of substrate to contacts on upper surface of build-up layers
Potential Applications
The technology described in this patent application could be applied in the development of advanced System on Chip (SoC) packages for various electronic devices, such as smartphones, tablets, and IoT devices.
Problems Solved
This technology solves the problem of efficiently integrating passive devices into SoC package substrates while maintaining a compact and reliable structure. It also addresses the challenge of connecting contacts on different surfaces of the substrate through build-up layers.
Benefits
The benefits of this technology include improved functionality and performance of SoC packages, increased design flexibility, enhanced reliability, and potentially reduced manufacturing costs.
Potential Commercial Applications
- Advanced SoC packages for smartphones
- High-performance SoC packages for tablets
- Compact SoC packages for IoT devices
Possible Prior Art
One possible prior art could be the use of traditional symmetric stackup structures in SoC package substrates, which may not offer the same level of integration and efficiency as the asymmetric stackup structure described in this patent application.
Unanswered Questions
How does this technology compare to existing solutions in terms of performance and cost?
The article does not provide a direct comparison with existing solutions in terms of performance and cost, leaving room for further analysis and evaluation.
What are the specific design considerations for implementing this technology in different types of electronic devices?
The article does not delve into the specific design considerations for implementing this technology in various electronic devices, which could vary based on factors such as size, power requirements, and functionality.
Original Abstract Submitted
An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
