18409397. DECODING ARCHITECTURE FOR WORD LINE TILES simplified abstract (Micron Technology, Inc.)

DECODING ARCHITECTURE FOR WORD LINE TILES

Organization Name

Micron Technology, Inc.

Inventor(s)

Paolo Fantini of Vimercate (IT)

Lorenzo Fratin of Buccinasco (IT)

Fabio Pellizzer of Boise ID (US)

Enrico Varesi of Milano (IT)

DECODING ARCHITECTURE FOR WORD LINE TILES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18409397 titled 'DECODING ARCHITECTURE FOR WORD LINE TILES

Simplified Explanation

The abstract describes a decoding architecture for memory devices, where word line plates of a memory array include a sheet of conductive material with multiple fingers for accessing memory cells. Memory cells coupled with a word line plate represent a logical page for accessing memory cells, and each word line plate is connected to a word line driver via an electrode. Memory cells are accessed by applying different voltages to the word line plate and pillar electrode.

• Word line plates with conductive material and fingers for accessing memory cells
• Logical pages represented by memory cells coupled with word line plates
• Connection between word line plates and word line drivers via electrodes
• Accessing memory cells by applying different voltages to word line plates and pillar electrodes

Potential Applications

This technology can be applied in various memory devices such as solid-state drives, computer memory modules, and embedded systems.

Problems Solved

This technology solves the problem of efficiently accessing and decoding memory cells within a memory array.

Benefits

The benefits of this technology include faster access times, improved memory management, and increased data retrieval speeds.

Potential Commercial Applications

Potential commercial applications of this technology include the manufacturing of high-speed memory devices for consumer electronics, data centers, and industrial applications.

Possible Prior Art

One possible prior art could be the use of similar decoding architectures in existing memory devices such as NAND flash memory or DRAM modules.

How does this technology impact power consumption in memory devices?

This article does not address the specific impact of this technology on power consumption in memory devices. It would be interesting to know if the new decoding architecture leads to any improvements in power efficiency.

Are there any limitations to the number of memory cells that can be accessed simultaneously using this architecture?

The article does not mention any limitations on the number of memory cells that can be accessed simultaneously. Understanding the scalability of this technology in terms of simultaneous access operations would be valuable information.

Original Abstract Submitted

Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.