18419015. SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES simplified abstract (Intel Corporation)

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES

Organization Name

Intel Corporation

Inventor(s)

Ehren Mannebach of Beaverton OR (US)

Aaron Lilak of Beaverton OR (US)

Hui Jae Yoo of Portland OR (US)

Patrick Morrow of Portland OR (US)

Anh Phan of Beaverton OR (US)

Willy Rachmady of Beaverton OR (US)

Cheng-Ying Huang of Portland OR (US)

Gilbert Dewey of Beaverton OR (US)

Rishabh Mehandru of Portland OR (US)

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18419015 titled 'SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES

Simplified Explanation

The abstract describes electronic systems with vias that have both horizontal and vertical portions to provide interconnects to stacked components.

• These systems allow for more efficient stacking of components in electronic devices.
• The vias provide a means of connecting the stacked components to the rest of the system.
• The horizontal and vertical portions of the vias enable complex interconnections within the system.

Potential Applications

The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, and computers where space-saving and efficient component stacking is crucial.

Problems Solved

This technology solves the problem of limited space in electronic devices by enabling the stacking of components in a more efficient manner. It also provides a solution for complex interconnections between stacked components.

Benefits

The benefits of this technology include increased efficiency in component stacking, improved interconnectivity, and potentially smaller and more compact electronic devices.

Potential Commercial Applications

The technology could be utilized in the consumer electronics industry for the development of smaller and more powerful devices. It could also be beneficial in industries where space-saving and efficient component stacking are essential.

Possible Prior Art

One possible prior art could be the use of through-silicon vias (TSVs) in semiconductor packaging to provide vertical interconnects between stacked components. Another could be the use of multi-layer printed circuit boards for complex interconnections in electronic systems.

Unanswered Questions

How does the technology described in the patent application compare to existing methods of component stacking in electronic devices?

The article does not provide a direct comparison between the technology described and existing methods, leaving room for further exploration of the advantages and disadvantages of each approach.

What are the potential challenges or limitations of implementing this technology in practical electronic devices?

The article does not address any potential challenges or limitations that may arise when implementing this technology, leaving room for further investigation into the practicality and feasibility of its application.

Original Abstract Submitted

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.