18517318. CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER simplified abstract (Intel Corporation)

CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER

Organization Name

Intel Corporation

Inventor(s)

Karthik Vaidyanathan of Berkeley CA (US)

Prasoonkumar Surti of Folsom CA (US)

Hugues Labbe of Folsom CA (US)

Atsuo Kuwahara of Portland OR (US)

Sameer Kp of Bangalore (IN)

Jonathan Kennedy of Bristol (GB)

Murali Ramadoss of Folsom CA (US)

Michael Apodaca of Folsom CA (US)

Abhishek Venkatesh of Hillsboro OR (US)

CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18517318 titled 'CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER

Simplified Explanation

The patent application describes technology that determines a stencil value to control the coarse pixel size of a graphics pipeline via a stencil buffer.

• The stencil value includes bits defining dimensions of the coarse pixel size.
• The technology allows for controlling the coarse pixel size on a per-pixel basis for multiple pixels.

Potential Applications

This technology could be applied in computer graphics, virtual reality systems, and augmented reality applications.

Problems Solved

This technology helps in optimizing the rendering process by controlling the coarse pixel size efficiently.

Benefits

The technology improves graphics rendering performance and quality by adjusting the coarse pixel size dynamically.

Potential Commercial Applications

Potential commercial applications include video game development, visual simulation software, and architectural visualization tools.

Possible Prior Art

Prior art may include patents related to graphics rendering optimization techniques and stencil buffer usage in computer graphics.

Unanswered Questions

How does this technology impact power consumption in graphics processing units (GPUs)?

The article does not address the potential impact of this technology on power consumption in GPUs. This could be a crucial factor for mobile devices and other power-constrained systems.

Are there any limitations to the scalability of this technology for high-resolution displays?

The article does not discuss any limitations that may arise when scaling this technology for use with high-resolution displays. This could be important for applications requiring ultra-high definition graphics.

Original Abstract Submitted

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.