18423166. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chung-Hao Tsai of Changhua County (TW)

Chen-Hua Yu of Hsinchu City (TW)

Chuei-Tang Wang of Taichung City (TW)

Wei-Ting Chen of Tainan City (TW)

Chien-Hsun Chen of Pingtung County (TW)

Shih-Ya Huang of Hsinchu City (TW)

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18423166 titled 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The semiconductor package described in the patent application includes a pair of dies, a redistribution structure, and a conductive plate. The dies are placed side by side, each with a contact pad. The redistribution structure connects the dies electrically and consists of an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. The conductive plate is connected to the contact pads of the dies and extends over the outermost dielectric layer and the pair of dies.

• Pair of dies placed side by side
• Redistribution structure electrically connects the dies
• Conductive plate connected to contact pads of the dies
• Innermost dielectric layer closer to the dies
• Outermost dielectric layer furthest from the dies
• Vertical projection of the conductive plate falls on spans of the dies

Potential Applications

This technology could be applied in semiconductor packaging for various electronic devices such as smartphones, tablets, and computers.

Problems Solved

This innovation helps in improving the electrical connectivity and reliability of semiconductor packages by providing a more efficient redistribution structure.

Benefits

The semiconductor package design enhances the performance and durability of electronic devices by ensuring better electrical connections between the dies.

Potential Commercial Applications

"Enhancing Electrical Connectivity in Semiconductor Packages for Improved Device Performance"

Possible Prior Art

There may be prior art related to semiconductor packaging techniques that focus on improving electrical connections and reliability within the package.

Unanswered Questions

How does this technology impact the overall size of the semiconductor package?

The article does not provide information on whether this innovation affects the size of the semiconductor package.

What are the specific electronic devices that could benefit the most from this technology?

The article does not specify which electronic devices would see the most significant improvements from implementing this semiconductor package design.

Original Abstract Submitted

Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.