18054161. BACKSIDE PROGRAMMABLE MEMORY simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

BACKSIDE PROGRAMMABLE MEMORY

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Albert M. Chu of Nashua NH (US)

Junli Wang of Slingerlands NY (US)

Albert M. Young of Fishkill NY (US)

Brent A. Anderson of Jericho VT (US)

Ruilong Xie of Niskayuna NY (US)

Carl Radens of LaGrangeville NY (US)

BACKSIDE PROGRAMMABLE MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18054161 titled 'BACKSIDE PROGRAMMABLE MEMORY

Simplified Explanation

Embodiments of the present invention involve processing methods and resulting structures with backside programmable memory cells. In one example, a front end of line structure is formed with programmable cells, each including a backside via in direct contact with a device region. The backside vias are divided into placeholder and programmed backside vias. A back end of line structure (word line) is formed on one surface, while a backside structure with backside metallization layer (bit line) is formed on the opposite surface.

• Front end of line structure with programmable cells
• Backside vias in direct contact with device region
• Placeholder and programmed backside vias
• Back end of line structure (word line)
• Backside structure with backside metallization layer (bit line)

Potential Applications

This technology could be applied in:

• Memory devices
• Integrated circuits
• Semiconductor manufacturing

Problems Solved

This innovation addresses issues related to:

• Memory cell programming
• Backside contact in semiconductor devices

Benefits

The benefits of this technology include:

• Increased memory cell programmability
• Enhanced device performance
• Improved manufacturing processes

Potential Commercial Applications

This technology has potential in:

• Consumer electronics
• Automotive electronics
• Industrial automation

Possible Prior Art

One possible prior art is the use of front-end and back-end structures in semiconductor devices for memory applications.

Unanswered Questions

How does this technology impact overall device reliability?

The article does not provide information on the reliability of devices using this technology. Further research and testing may be needed to determine the impact on device reliability.

What are the potential challenges in scaling this technology for mass production?

The article does not address the scalability of this technology for mass production. It is important to consider the challenges that may arise when implementing this technology on a larger scale.

Original Abstract Submitted

Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.