17988507. COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
Contents
- 1 COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
BLAINE JEFFREY Gross of ESSEX JUNCTION VT (US)
RICHARD ANDRE Wachnik of MOUNT KISCO NY (US)
COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17988507 titled 'COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS
Simplified Explanation
The abstract describes a method for directly measuring the timing window of a latch in a ring oscillator circuit by providing signals with predetermined delay times, generating clock signals, and determining the state of the ring oscillator circuit.
- Providing signals with predetermined delay times to a latch in a ring oscillator circuit
- Generating clock signals based on the received signals
- Determining the state of the ring oscillator circuit based on the output
Potential Applications
This technology can be applied in the field of integrated circuit design for optimizing latch timing windows in digital circuits.
Problems Solved
This technology helps in accurately measuring latch timing windows, which is crucial for ensuring the proper functioning of digital circuits.
Benefits
- Improved accuracy in measuring latch timing windows - Enhanced performance of digital circuits - Efficient optimization of integrated circuit designs
Potential Commercial Applications
Optimizing latch timing windows in digital circuits for improved performance and reliability.
Possible Prior Art
There may be prior art related to measuring latch timing windows in digital circuits using different methods or techniques.
Unanswered Questions
How does this method compare to traditional methods of measuring latch timing windows?
This article does not provide a comparison between this method and traditional methods of measuring latch timing windows.
What are the limitations of this technology in real-world applications?
The article does not discuss the potential limitations of implementing this technology in practical integrated circuit designs.
Original Abstract Submitted
Direct measurement of a latch timing window includes, for each of a plurality of predetermined delay times: providing a first signal to a data input of a first latch of a ring oscillator circuit via a delay block configured to delay the first signal by the predetermined delay time; providing the first signal to a first logic clock buffer (LCB); generating a clock signal by the first LCB responsive to receiving the first signal; providing the clock signal to a clock input of the first latch; and determining from an output of the ring oscillator circuit that the ring oscillator circuit is in either an oscillating state or a non-oscillating state. At least one timing window parameter for the first latch is determined based on one or more of the plurality of delay times that are associated with an oscillating state of the ring oscillator circuit.
