18054194. STACKED FET WITH EXTREMELY SMALL CELL HEIGHT simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

STACKED FET WITH EXTREMELY SMALL CELL HEIGHT

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

Chen Zhang of Guilderland NY (US)

Albert M. Young of Fishkill NY (US)

Brent A. Anderson of Jericho VT (US)

Kisik Choi of Watervliet NY (US)

Junli Wang of Slingerlands NY (US)

STACKED FET WITH EXTREMELY SMALL CELL HEIGHT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18054194 titled 'STACKED FET WITH EXTREMELY SMALL CELL HEIGHT

Simplified Explanation

The microelectronic structure described in the abstract includes a first stacked FET device with a first bottom FET device and a first upper FET device. The first bottom FET device has multiple bottom channel layers, while the first upper FET device has multiple upper channel layers. The structure also features a bottom gate surrounding the bottom channel layers and an upper gate surrounding the upper channel layers. A gate protrusion extends downward from the backside of the upper gate to connect to the bottom gate, partially overlapping with the bottom gate cut region of the first bottom stacked FET device and the upper gate cut region of the first upper stacked FET device.

• The microelectronic structure includes a first stacked FET device with a first bottom FET device and a first upper FET device.
• The first bottom FET device has multiple bottom channel layers, and the first upper FET device has multiple upper channel layers.
• The structure features a bottom gate surrounding the bottom channel layers and an upper gate surrounding the upper channel layers.
• A gate protrusion extends downward from the backside of the upper gate to connect to the bottom gate.
• The gate protrusion partially overlaps with the bottom gate cut region of the first bottom stacked FET device and the upper gate cut region of the first upper stacked FET device.

Potential Applications

This technology could be applied in:

• Advanced semiconductor devices
• High-performance electronics

Problems Solved

This technology helps in:

• Enhancing device performance
• Improving integration capabilities

Benefits

The benefits of this technology include:

• Increased efficiency
• Enhanced functionality

Potential Commercial Applications

This technology could be used in:

• Semiconductor manufacturing industry
• Electronics research and development

Possible Prior Art

One possible prior art for this technology could be:

• Stacked FET devices with gate protrusions

Unanswered Questions

How does the gate protrusion impact the overall performance of the microelectronic structure?

The impact of the gate protrusion on the performance of the microelectronic structure is not explicitly discussed in the abstract. Further research or experimentation may be needed to determine the exact effects.

What are the specific manufacturing processes involved in creating the gate protrusion in the microelectronic structure?

The abstract does not provide details on the manufacturing processes used to create the gate protrusion. Understanding these processes could be crucial for replicating or improving upon this technology.

Original Abstract Submitted

A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.