DIGITAL PIXEL ARCHITECTURE SUPPORTING RE-USE OF COMPONENTS FOR IN-PIXEL ANALOG-TO-DIGITAL CONVERSION OF INTEGRATION RESIDUE

Abstract: a system includes a focal plane array having multiple pixel circuit elements. each pixel circuit element includes a photodetector configured to generate an electrical current based on received illumination. each pixel circuit element also includes an integration capacitor configured to be charged by the electrical current and generate a capacitor voltage and to be discharged. each pixel circuit element further includes a comparator configured to generate pulses in a digital output based on the capacitor voltage of the integration capacitor. in addition, each pixel circuit element includes a counter configured to (i) in a first configuration, count the pulses in the digital output of the comparator during a sampling period and (ii) in a second configuration, count pulses in a clock signal during a residue digitization period. a counted number of pulses in the clock signal is indicative of a residue stored on the integration capacitor at an end of the sampling period.

Inventor(s): Eric J. Beuville, Joshua J. Cantrell, Micky R. Harris

CPC Classification: H04N25/772 (comprising A/D, V/T, V/F, I/T or I/F converters)

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