SPARSE MATRIX MULTIPLICATION

Abstract: a processor and method for efficiently implementing matrix multiplication. the processor comprises: a first register (vc) for storing elements of an input vector (x); a second register (vb) for storing a plurality of index tuples, each index tuple comprising at least an input index addressing an element of the input vector (x) in the first register (vc); an output register (va) comprising a plurality of accumulators for storing elements of an output vector (v); a vector unit configured to execute each index tuple in the second register (vb) in parallel by, for each index tuple: i) generating a respective result value by multiplying the element of the input vector (x) in the first register (vc) addressed by the input index of that index tuple by a corresponding kernel weight in a memory; and ii) adding the result value for that index tuple to one of the accumulators in the output register (va).

Inventor(s): Hendrik Lambertus MULLER, Andrew STANFORD-JASON

CPC Classification: G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition )})

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