International business machines corporation (20240162229). STACKED FET WITH EXTREMELY SMALL CELL HEIGHT simplified abstract

STACKED FET WITH EXTREMELY SMALL CELL HEIGHT

Organization Name

international business machines corporation

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

Chen Zhang of Guilderland NY (US)

Albert M. Young of Fishkill NY (US)

Brent A. Anderson of Jericho VT (US)

Kisik Choi of Watervliet NY (US)

Junli Wang of Slingerlands NY (US)

STACKED FET WITH EXTREMELY SMALL CELL HEIGHT - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240162229 titled 'STACKED FET WITH EXTREMELY SMALL CELL HEIGHT

Simplified Explanation

The microelectronic structure described in the abstract consists of a first stacked FET device with a first bottom FET device and a first upper FET device. The first bottom FET device includes multiple bottom channel layers, while the first upper FET device includes multiple upper channel layers. The structure also features a bottom gate surrounding the bottom channel layers and an upper gate surrounding the upper channel layers. A gate protrusion extends downwards from the backside of the upper gate to connect to the bottom gate, partially overlapping with the bottom gate cut region of the first bottom stacked FET device and the upper gate cut region of the first upper stacked FET device.

• The microelectronic structure includes a first stacked FET device with both bottom and upper FET devices.
• The first bottom FET device contains multiple bottom channel layers, while the first upper FET device contains multiple upper channel layers.
• The structure features a bottom gate surrounding the bottom channel layers and an upper gate surrounding the upper channel layers.
• A gate protrusion extends downwards from the backside of the upper gate to connect to the bottom gate.
• The gate protrusion partially overlaps with the bottom gate cut region of the first bottom stacked FET device and the upper gate cut region of the first upper stacked FET device.

Potential Applications

The technology described in the patent application could have potential applications in:

• Semiconductor manufacturing
• Integrated circuits
• Electronics industry

Problems Solved

This technology helps in:

• Improving the performance of FET devices
• Enhancing the efficiency of microelectronic structures
• Reducing power consumption in electronic devices

Benefits

The benefits of this technology include:

• Increased functionality of microelectronic devices
• Higher performance levels
• Improved energy efficiency

Potential Commercial Applications

A potential commercial application of this technology could be in:

• Advanced electronic devices
• High-performance computing systems
• Next-generation mobile devices

Possible Prior Art

One possible prior art related to this technology is the development of stacked FET devices with multiple channel layers for improved performance and efficiency.

How does this technology compare to traditional FET devices in terms of performance and efficiency?

This article does not provide a direct comparison between the new technology and traditional FET devices.

What are the specific manufacturing processes involved in creating the gate protrusion and overlapping regions in the microelectronic structure?

The article does not delve into the detailed manufacturing processes involved in creating the gate protrusion and overlapping regions.

Original Abstract Submitted

a microelectronic structure including a first stacked fet device that includes a first bottom fet device and a first upper fet device. the first bottom fet device include a plurality of first bottom channel layers, and the first upper fet device includes a plurality of first upper channel layers. a bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. a gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. the gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked fet device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked fet device.