NVIDIA Corporation patent applications on May 16th, 2024
Patent Applications by NVIDIA Corporation on May 16th, 2024
NVIDIA Corporation: 27 patent applications
NVIDIA Corporation has applied for patents in the areas of G06N3/08 (10), G06T1/60 (8), G06T1/20 (8), G06T2207/20084 (7), G06T7/11 (6)
With keywords such as: image, neural, scene, techniques, systems, generate, learning, data, images, and machine in patent application abstracts.
Patent Applications by NVIDIA Corporation
Inventor(s): Sammy Joe Christen of Luzern (CH) for nvidia corporation, Wei Yang of Lake Forest Park WA (US) for nvidia corporation, Claudia Perez D'Arpino of Seattle WA (US) for nvidia corporation, Dieter Fox of Seattle WA (US) for nvidia corporation, Yu-Wei Chao of Redmond WA (US) for nvidia corporation
IPC Code(s): B25J9/16, G05B19/4155, G06N3/08
Abstract: apparatuses, systems, and techniques to control a real-world and/or virtual device (e.g., a robot). in at least one embodiment, the device is controlled based, at least in part on, for example, one or more neural networks. parameter values for the neural network(s) may be obtained by training the neural network(s) to control movement of a first agent with respect to at least one first target while avoiding collision with at least one stationary first holder of the at least one first target, and updating the parameter values by training the neural network(s) to control movement of a second agent with respect to at least one second target while avoiding collision with at least one non-stationary second holder of the at least one second target.
20240160368.SELECTING SOLID STATE DEVICES FOR DATA STORAGE_simplified_abstract_(nvidia corporation)
Inventor(s): Shirish Bahirat of Longmont CO (US) for nvidia corporation
IPC Code(s): G06F3/06, G06F12/12
Abstract: apparatuses, systems, and techniques for selecting and/or managing memory devices. in at least one embodiment, a personality type may be obtained for data stored in a cache, and the data may be transferred to at least one region of at least one memory device having the personality type.
Inventor(s): Rangharajan Venkatesan of Sunnyvale CA (US) for nvidia corporation, Reena Elangovan of West Lafayette IN (US) for nvidia corporation, Charbel Sakr of ¿San Jose CA (US) for nvidia corporation, Brucek Kurdo Khailany of Rollingwood TX (US) for nvidia corporation, Ming Y Siu of Santa Clara CA (US) for nvidia corporation, Ilyas Elkin of Sunnyvale CA (US) for nvidia corporation, Brent Ralph Boswell of Aloha OR (US) for nvidia corporation
IPC Code(s): G06F7/487, G06F7/499
Abstract: mechanisms to exploit the inherent resiliency of deep learning inference workloads to improve the energy efficiency of computer processors such as graphics processing units with these workloads. the mechanisms provide energy-accuracy tradeoffs in the computation of deep learning inference calculations via energy-efficient floating point data path micro-architectures with integer accumulation, and enhanced mechanisms for per-vector scaled quantization (vs-quant) of floating-point arguments.
20240160491.RESOURCE PREDICTION FOR WORKLOADS_simplified_abstract_(nvidia corporation)
Inventor(s): Rohit Taneja of Fremont CA (US) for nvidia corporation, Siddha Ganju of Santa Clara CA (US) for nvidia corporation, Kash Krishna of San Jose CA (US) for nvidia corporation, Brian Carpenter of Frisco TX (US) for nvidia corporation
IPC Code(s): G06F9/50
Abstract: apparatuses, systems, and techniques to use one or more neural networks to predict one or more computing resources to perform one or more workloads are described.
Inventor(s): Davis Winston Rempe of Redwood CA (US) for nvidia corporation, Karsten Julian Kreis of Vancouver (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation, Jonah Philion of Toronto (CA) for nvidia corporation
IPC Code(s): G06N3/02
Abstract: in various examples, systems and methods are disclosed relating to neural networks for realistic and controllable agent simulation using guided trajectories. the neural networks can be configured using training data including trajectories and other state data associated with subjects or agents and remote or neighboring subjects or agents, as well as context data representative of an environment in which the subjects are present. the trajectories can be determining using the neural networks and using various forms of guidance for controllability, such as for waypoint navigation, obstacle avoidance, and group movement.
20240160905.TECHNIQUES FOR COMPRESSING NEURAL NETWORKS_simplified_abstract_(nvidia corporation)
Inventor(s): Chong Yu of Shanghai (CN) for nvidia corporation
IPC Code(s): G06N3/0495, G06N3/045
Abstract: apparatuses, systems, and techniques to compress neural networks. in at least one embodiment, one or more first neural networks are used to cause one or more compressed neural networks to be selected based, at least in part, on accuracy and performance of the one or more compressed neural networks.
Inventor(s): Ryan Cosner of Altadena CA (US) for nvidia corporation, Yuxiao Chen of Newark CA (US) for nvidia corporation, Karen Yan Ming Leung of Los Altos CA (US) for nvidia corporation, Marco Pavone of Stanford CA (US) for nvidia corporation
IPC Code(s): G06N3/08
Abstract: in various examples, learning responsibility allocations for machine interactions is described herein. systems and methods are disclosed that train a neural network(s) to generate outputs indicating estimated levels of responsibilities associated with interactions between vehicles or machines and other objects (e.g., other vehicles, machines, pedestrians, animals, etc.). in some examples, the neural network(s) is trained using real-world data, such as data representing scenes depicting actual interactions between vehicles and objects and/or parameters (e.g., velocities, positions, directions, etc.) associated with the interactions. then, in practice, a vehicle (e.g., an autonomous vehicle, a semi-autonomous vehicle, etc.) may use the neural network(s) to generate an output indicating a proposed or estimated level of responsibility associated with an interaction between the vehicle and an object. the vehicle may then use the output to determine one or more controls for the vehicle to use when navigating.
20240160932.TECHNIQUES FOR PRUNING NEURAL NETWORKS_simplified_abstract_(nvidia corporation)
Inventor(s): Yue Zhu of Shanghai (CN) for nvidia corporation
IPC Code(s): G06N3/082, G06N3/0464, G06N3/10
Abstract: apparatuses, systems, and techniques to prune neural networks. in at least one embodiment, one or more portions of a neural network are deactivated based, at least in part, on less than all previously evaluated portions of the neural network.
Inventor(s): Aki Petteri Niemi of Vancouver (CA) for nvidia corporation, Sean Midthun Pieper of Waldport OR (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F13/24, G06T1/60
Abstract: disclosed are apparatuses, systems, and techniques that implementing fractionalized data transfers between processing devices in real-time data generating and streaming applications. the techniques include but are not limited to processing, by a first processing device, an image data to generate a plurality of portions of an image, responsive to generating a first portion of the plurality of portions of the image, storing the first portion in a first memory device of the first processing device, setting a completion indicator for the first portion, and causing the first portion to be provided to a second processing device.
Inventor(s): Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation, Alexander Lev Minkin of Los Altos CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore (IN) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stäfa (CH) for nvidia corporation, Aditya Avinash Atluri of Redmond WA (US) for nvidia corporation, Apoorv Parle of Santa Clara CA (US) for nvidia corporation, Ronny Meir Krashinsky of Portola Valley CA (US) for nvidia corporation, Alan Kaatz of Seattle WA (US) for nvidia corporation, Andrew Robert Kerr of Atlanta GA (US) for nvidia corporation, Jack H. Choquette of Palo Alto CA (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F9/54, G06F17/16, G06T1/60
Abstract: apparatuses, systems, and techniques to indicate how to generate image-to-column transformations. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to indicate how to generate one or more image-to-column transformations.
Inventor(s): Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation, Alexander Lev Minkin of Los Altos CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore (IN) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stäfa (CH) for nvidia corporation, Aditya Avinash Atluri of Redmond WA (US) for nvidia corporation, Apoorv Parle of Santa Clara CA (US) for nvidia corporation, Chao Li of Austin TX (US) for nvidia corporation, Ronny Meir Krashinsky of Portola Valley CA (US) for nvidia corporation, Alan Kaatz of Seattle WA (US) for nvidia corporation, Andrew Robert Kerr of Atlanta GA (US) for nvidia corporation, Jack H. Choquette of Palo Alto CA (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F9/54, G06T1/60
Abstract: apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause a first tensor to be translated into a second tensor according to a tensor map.
Inventor(s): Harold Carter Edwards of Campbell CA (US) for nvidia corporation, Stephen Anthony Bernard Jones of San Francisco CA (US) for nvidia corporation, Alexander Lev Minkin of Los Altos CA (US) for nvidia corporation, Olivier Giroux of Santa Clara CA (US) for nvidia corporation, Gokul Ramaswamy Hirisave Chandra Shekhara of Bangalore (IN) for nvidia corporation, Vishalkumar Ketankumar Mehta of Stäfa (CH) for nvidia corporation, Aditya Avinash Atluri of Redmond WA (US) for nvidia corporation, Apoorv Parle of Santa Clara CA (US) for nvidia corporation, Chao Li of Austin TX (US) for nvidia corporation, Ronny Meir Krashinsky of Portola Valley CA (US) for nvidia corporation, Alan Kaatz of Seattle WA (US) for nvidia corporation, Andrew Robert Kerr of Atlanta GA (US) for nvidia corporation, Jack H. Choquette of Palo Alto CA (US) for nvidia corporation
IPC Code(s): G06T1/20, G06F9/54, G06T1/60
Abstract: apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map without storing information about a memory transaction corresponding to the translation. in at least one embodiment, one or more circuits are to perform an application programming interface (api) to cause a first tensor to be translated into a second tensor according to a tensor map without storing information about one or more memory transactions corresponding to the translation.
Inventor(s): Yogesh BALAJI of Mountain View CA (US) for nvidia corporation, Timo Oskari AILA of Tuusula (FI) for nvidia corporation, Miika AITTALA of Tuusula (FI) for nvidia corporation, Bryan CATANZARO of Los Altos Hills CA (US) for nvidia corporation, Xun HUANG of Mountain View CA (US) for nvidia corporation, Tero Tapani KARRAS of Helsinki (FI) for nvidia corporation, Karsten KREIS of Vancouver (CA) for nvidia corporation, Samuli LAINE of Vantaa (FI) for nvidia corporation, Ming-Yu LIU of San Jose CA (US) for nvidia corporation, Seungjun NAH of Santa Clara CA (US) for nvidia corporation, Jiaming SONG of San Carlos CA (US) for nvidia corporation, Arash VAHDAT of San Mateo CA (US) for nvidia corporation, Qinsheng ZHANG of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T5/00
Abstract: techniques are disclosed herein for generating a content item. the techniques include performing one or more first denoising operations based on an input and a first machine learning model to generate a first content item, and performing one or more second denoising operations based on the input, the first content item, and a second machine learning model to generate a second content item, where the first machine learning model is trained to denoise content items having an amount of corruption within a first corruption range, the second machine learning model is trained to denoise content items having an amount of corruption within a second corruption range, and the second corruption range is lower than the first corruption range.
Inventor(s): Wentao Zhu of Mountain View CA (US) for nvidia corporation, Daguang Xu of Potomac MD (US) for nvidia corporation, Andriy Myronenko of San Mateo CA (US) for nvidia corporation, Ziyue Xu of Reston VA (US) for nvidia corporation
IPC Code(s): G06T7/00, G06F30/20, G06N3/08, G06T7/11, G06T7/33
Abstract: apparatuses, systems, and techniques to perform registration among images. in at least one embodiment, one or more neural networks are trained to indicate registration of features in common among at least two images by generating a first correspondence by simulating a registration process of registering an image and applying the at least two images and the first correspondence to a neural network to derive a second correspondence of the features in common among the at least two images.
Inventor(s): Wentao Zhu of Mountain View CA (US) for nvidia corporation, Daguang Xu of Potomac MD (US) for nvidia corporation, Andriy Myronenko of San Mateo CA (US) for nvidia corporation, Ziyue Xu of Reston VA (US) for nvidia corporation
IPC Code(s): G06T7/00, G06F30/20, G06N3/08, G06T7/11, G06T7/33
Abstract: apparatuses, systems, and techniques to perform registration among images. in at least one embodiment, one or more neural networks are trained to indicate registration of features in common among at least two images by generating a first correspondence by simulating a registration process of registering an image and applying the at least two images and the first correspondence to a neural network to derive a second correspondence of the features in common among the at least two images.
Inventor(s): Ayon Sen of Santa Clara CA (US) for nvidia corporation, Gang Pan of Fremont CA (US) for nvidia corporation, Cheng-Chieh Yang of Seattle WA (US) for nvidia corporation, Yue Wu of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06T7/80
Abstract: in various examples, sensor configuration for autonomous or semi-autonomous systems and applications is described. systems and methods are disclosed that may use image feature correspondences between camera images along with an assumption that image features are locally planar to determine parameters for calibrating an image sensor with a lidar sensor and/or another image sensor. in some examples, an optimization problem is constructed that attempts to minimize a geometric loss function, where the geometric loss function encodes the notion that corresponding image features are views of a same point on a locally planar surface (e.g., a surfel or mesh) that is constructed from lidar data generated using a lidar sensor. in some examples, performing such processes to determine the calibration parameters may remove structure estimation from the optimization problem.
Inventor(s): Ayon Sen of Santa Clara CA (US) for nvidia corporation, Gang Pan of Fremont CA (US) for nvidia corporation, Cheng-Chieh Yang of Seattle WA (US) for nvidia corporation, Yue Wu of Mountain View CA (US) for nvidia corporation
IPC Code(s): G06T7/80, G01S17/86, G01S17/89, G01S17/931, H04N17/00
Abstract: in various examples, sensor configuration for autonomous or semi-autonomous systems and applications is described. systems and methods are disclosed that may use image feature correspondences between camera images along with an assumption that image features are locally planar to determine parameters for calibrating an image sensor with a lidar sensor and/or another image sensor. in some examples, an optimization problem is constructed that attempts to minimize a geometric loss function, where the geometric loss function encodes the notion that corresponding image features are views of a same point on a locally planar surface (e.g., a surfel or mesh) that is constructed from lidar data generated using a lidar sensor. in some examples, performing such processes to determine the calibration parameters may remove structure estimation from the optimization problem.
Inventor(s): Zhengyi Luo of Pittsburgh PA (US) for nvidia corporation, Jason Peng of Vancouver (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Or Litany of Sunnyvale CA (US) for nvidia corporation, Davis Winston Rempe of Redwood City CA (US) for nvidia corporation, Ye Yuan of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G06T13/40, G06N3/006
Abstract: in various examples, systems and methods are disclosed relating to generating a simulated environment and update a machine learning model to move each of a plurality of human characters having a plurality of body shapes, to follow a corresponding trajectory within the simulated environment as conditioned on a respective body shape. the simulated human characters can have diverse characteristics (such as gender, body proportions, body shape, and so on) as observed in real-life crowds. a machine learning model can determine an action for a human character in a simulated environment, based at least on a humanoid state, a body shape, and task-related features. the task-related features can include an environmental feature and a trajectory.
Inventor(s): Yang FU of San Diego CA (US) for nvidia corporation, Sifei LIU of San Diego CA (US) for nvidia corporation, Jan KAUTZ of Lexington MA (US) for nvidia corporation, Xueting LI of Santa Clara CA (US) for nvidia corporation, Shalini DE MELLO of San Francisco CA (US) for nvidia corporation, Amey KULKARNI of San Jose CA (US) for nvidia corporation, Milind NAPHADE of Cupertino CA (US) for nvidia corporation
IPC Code(s): G06T15/04, G06T7/50, G06T9/00
Abstract: in various embodiments, a scene reconstruction model generates three-dimensional (3d) representations of scenes. the scene reconstruction model maps a first red, blue, green, and depth (rgbd) image associated with both a first scene and a first viewpoint to a first surface representation of at least a first portion of the first scene. the scene reconstruction model maps a second rgbd image associated with both the first scene and a second viewpoint to a second surface representation of at least a second portion of the first scene. the scene reconstruction model aggregates at least the first surface representation and the second surface representation in a 3d space to generate a first fused surface representation of the first scene. the scene reconstruction model maps the first fused surface representation of the first scene to a 3d representation of the first scene.
Inventor(s): Jeevan Devaranjan of Toronto (CA) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Amlan Kar of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/00, A63F13/52, G06F16/51, G06F16/54, G06N3/08, G06N5/025, G06N7/01, G06T15/20, G06V10/25, G06V10/774, G06V20/20
Abstract: a rule set or scene grammar can be used to generate a scene graph that represents the structure and visual parameters of objects in a scene. a renderer can take this scene graph as input and, with a library of content for assets identified in the scene graph, can generate a synthetic image of a scene that has the desired scene structure without the need for manual placement of any of the objects in the scene. images or environments synthesized in this way can be used to, for example, generate training data for real world navigational applications, as well as to generate virtual worlds for games or virtual reality experiences.
20240161403.HIGH RESOLUTION TEXT-TO-3D CONTENT CREATION_simplified_abstract_(nvidia corporation)
Inventor(s): Chen-Hsuan Lin of Santa Clara CA (US) for nvidia corporation, Tsung-Yi Lin of Sunnyvale CA (US) for nvidia corporation, Ming-Yu Liu of San Jose CA (US) for nvidia corporation, Sanja Fidler of Toronto (CA) for nvidia corporation, Karsten Kreis of Vancouver (CA) for nvidia corporation, Luming Tang of New York NY (US) for nvidia corporation, Xiaohui Zeng of Toronto (CA) for nvidia corporation, Jun Gao of Toronto (CA) for nvidia corporation, Xun Huang of Mountain View CA (US) for nvidia corporation, Towaki Takikawa of Toronto (CA) for nvidia corporation
IPC Code(s): G06T17/20, G06T3/40, G06T15/04, G06T17/00, G06T19/20
Abstract: text-to-image generation generally refers to the process of generating an image from one or more text prompts input by a user. while artificial intelligence has been a valuable tool for text-to-image generation, current artificial intelligence-based solutions are more limited as it relates to text-to-3d content creation. for example, these solutions are oftentimes category-dependent, or synthesize 3d content at a low resolution. the present disclosure provides a process and architecture for high-resolution text-to-3d content creation.
Inventor(s): Yang FU of San Diego CA (US) for nvidia corporation, Sifei LIU of San Diego CA (US) for nvidia corporation, Jan KAUTZ of Lexington MA (US) for nvidia corporation, Xueting LI of Santa Clara CA (US) for nvidia corporation, Shalini DE MELLO of San Francisco CA (US) for nvidia corporation, Amey KULKARNI of San Jose CA (US) for nvidia corporation, Milind NAPHADE of Cupertino CA (US) for nvidia corporation
IPC Code(s): G06T17/20
Abstract: in various embodiments, a training application trains a machine learning model to generate three-dimensional (3d) representations of two-dimensional images. the training application maps a depth image and a viewpoint to signed distance function (sdf) values associated with 3d query points. the training application maps a red, blue, and green (rgb) image to radiance values associated with the 3di query points. the training application computes a red, blue, green, and depth (rgbd) reconstruction loss based on at least the sdf values and the radiance values. the training application modifies at least one of a pre-trained geometry encoder, a pre-trained geometry decoder, an untrained texture encoder, or an untrained texture decoder based on the rgbd reconstruction loss to generate a trained machine learning model that generates 3d representations of rgbd images.
Inventor(s): Xueting LI of Santa Clara CA (US) for nvidia corporation, Stanley BIRCHFIELD of Sammamish WA (US) for nvidia corporation, Shalini DE MELLO of San Francisco CA (US) for nvidia corporation, Sifei LIU of Santa Clara CA (US) for nvidia corporation, Jiaming SONG of San Carlos CA (US) for nvidia corporation, Yufei YE of Pittsburgh PA (US) for nvidia corporation
IPC Code(s): G06V10/774, G06T5/00, G06T7/11, G06V10/82, G06V40/10
Abstract: techniques are disclosed herein for generating an image. the techniques include performing one or more first denoising operations based on a first machine learning model and an input image that includes a first object to generate a mask that indicates a spatial arrangement associated with a second object interacting with the first object, and performing one or more second denoising operations based on a second machine learning model, the input image, and the mask to generate an image of the second object interacting with the first object.
Inventor(s): Subhankar Ghosh of Santa Clara CA (US) for nvidia corporation, Boris Ginsburg of Sunnyvale CA (US) for nvidia corporation
IPC Code(s): G10L13/047, G10L13/08, G10L25/18, G10L25/30
Abstract: disclosed are apparatuses, systems, and techniques that may use machine learning for generating artificial speech. the techniques include obtaining a synthetic embedding using learned embeddings associated with different speakers. at least one learned embedding may be generated using a multi-stage training of a machine learning model (mlm) with progressively increasing quality of training speech utterances. the techniques may further include using the mlm and the synthetic embedding to generate synthetic audio data.
Inventor(s): Gal Chechik of Ramat Hasharon (IL) for nvidia corporation, Shie Mannor of HAIFA (IL) for nvidia corporation
IPC Code(s): G10L15/26, G06V10/774, G10L15/22
Abstract: a system to generate a latent space model of a scene or video and apply this latent space and candidate sentences formed from digital audio to a vision-language matching model to enhance the accuracy of speech-to-text conversion. a latent space embedding of the scene is generated in which similar features are represented in the space closer to one another. an embedding for the digital audio is also generated. the vision-language matching model utilizes the latent space embedding to enhance the accuracy of transcribing/interpreting the embedding of the digital audio.
Inventor(s): Mahmut Ersin Sinangil of Los Altos CA (US) for nvidia corporation, Sudhir Shrikantha Kudva of Dublin CA (US) for nvidia corporation, Nikola Nedovic of San Jose CA (US) for nvidia corporation, Carl Thomas Gray of Apex NC (US) for nvidia corporation
IPC Code(s): G11C7/24, G11C7/10, G11C7/20
Abstract: puf cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different v/t conditions and different uses over time in noisy environments. the puf cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. a set of such puf cells utilized to generate a device-specific bit pattern, for example a master key.
20240161815.DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE_simplified_abstract_(nvidia corporation)
Inventor(s): Lalit Gupta of FREMONT CA (US) for nvidia corporation, Jason Golbus of Palo Alto CA (US) for nvidia corporation, Jesse San-Jey Wang of Santa Clara CA (US) for nvidia corporation
IPC Code(s): G11C11/4096, G11C11/4076, G11C11/4094
Abstract: multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.
- NVIDIA Corporation
- B25J9/16
- G05B19/4155
- G06N3/08
- Nvidia corporation
- G06F3/06
- G06F12/12
- G06F7/487
- G06F7/499
- G06F9/50
- G06N3/02
- G06N3/0495
- G06N3/045
- G06N3/082
- G06N3/0464
- G06N3/10
- G06T1/20
- G06F13/24
- G06T1/60
- G06F9/54
- G06F17/16
- G06T5/00
- G06T7/00
- G06F30/20
- G06T7/11
- G06T7/33
- G06T7/80
- G01S17/86
- G01S17/89
- G01S17/931
- H04N17/00
- G06T13/40
- G06N3/006
- G06T15/04
- G06T7/50
- G06T9/00
- G06T17/00
- A63F13/52
- G06F16/51
- G06F16/54
- G06N5/025
- G06N7/01
- G06T15/20
- G06V10/25
- G06V10/774
- G06V20/20
- G06T17/20
- G06T3/40
- G06T19/20
- G06V10/82
- G06V40/10
- G10L13/047
- G10L13/08
- G10L25/18
- G10L25/30
- G10L15/26
- G10L15/22
- G11C7/24
- G11C7/10
- G11C7/20
- G11C11/4096
- G11C11/4076
- G11C11/4094
- G06T2207/20084
