18494023. PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIENTED INTEGRATED CIRCUIT DIES (Intel Corporation)
PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIENTED INTEGRATED CIRCUIT DIES
Organization Name
Inventor(s)
Rajiv Mongia of Portland OR US
Sagar Suthram of Portland OR US
Wilfred Gomes of Portland OR US
Ravindranath Vithal Mahajan of Chandler AZ US
Nicolas Butzen of Portland OR US
PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIENTED INTEGRATED CIRCUIT DIES
This abstract first appeared for US patent application 18494023 titled 'PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIENTED INTEGRATED CIRCUIT DIES
Original Abstract Submitted
Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.
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