18985089. LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)

LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor(s)

ZHE-WEI Jiang of HSINCHU CITY TW

JERRY CHANG JUI Kao of TAIPEI CITY TW

SUNG-YEN Yeh of PINGTUNG COUNTY TW

LI CHUNG Hsu of HSINCHU CITY TW

LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION

This abstract first appeared for US patent application 18985089 titled 'LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION

Original Abstract Submitted

A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout including a cell and a layout context in a vicinity of the cell; determining a representative context group for the cell from a set of predetermined context groups; determining a representative timing table corresponding to the representative context group, the representative timing table including a best-case delay value and a worst-case delay value; and performing a timing analysis on the layout according to the best-case delay value and the worst-case delay value.