18485461. AUTOMATIC CLOCK-GATING INSERTION IN REGISTER-TRANSFER LEVEL DESIGN (International Business Machines Corporation)

AUTOMATIC CLOCK-GATING INSERTION IN REGISTER-TRANSFER LEVEL DESIGN

Organization Name

International Business Machines Corporation

Inventor(s)

Maya Safieddine of Pflugerville TX US

David John Geiger of Poughkeepsie NY US

Ali S. El-zein of Austin TX US

Viresh Paruthi of Austin TX US

AUTOMATIC CLOCK-GATING INSERTION IN REGISTER-TRANSFER LEVEL DESIGN

This abstract first appeared for US patent application 18485461 titled 'AUTOMATIC CLOCK-GATING INSERTION IN REGISTER-TRANSFER LEVEL DESIGN

Original Abstract Submitted

A computer-implemented method for inserting clock-gating in a register-transfer level (RTL) design is provided. The computer-implemented method includes flattening the RTL design, identifying modules and state elements in the RTL design, computing a clock-gating expression for each of the state elements of the RTL design, selecting terms of the clock-gating expression for each one of the state elements that is traceable to signals in a same one of the modules as the one of the state elements, determining which clock-gating terms are equivalent to those of other state elements in the RTL design, clustering state elements with equivalent clock-gating terms into clusters and inserting clock-gating logic, which equates to the equivalent clock-gating terms, into the RTL design for each cluster.