TEST ARCHITECTURE FOR 3D STACKED CIRCUITS: abstract simplified (17700329)

In this abstract, the concept of stacked circuits is introduced. Stacked circuits are designed to make post-stacking testing easier. The abstract describes an example of a stacked circuit that consists of two dies connected through multiple interconnects. The first die has various components, including a test input interface to receive test data signals and a source test clock signal, a test output interface to transmit test responses, a first test signal path, and interfaces to communicate with the second die. The communication between the two dies is facilitated by a low-latency clock path. The abstract concludes by mentioning that there are other aspects, embodiments, and features included in stacked circuits.