18125348. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Sung Keun Park of Suwon-si (KR)
Seong-Hoon Bae of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18125348 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The abstract describes a semiconductor package that includes a first substrate, a semiconductor chip mounted on the first substrate, a second substrate spaced apart from the first substrate, a wire connecting the first substrate to the second substrate, a mold structure covering the top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and the lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire between the wire and the mold structure.
- The semiconductor package consists of multiple components, including substrates, a semiconductor chip, a wire, a mold structure, and an under-fill pattern.
- The first substrate serves as a base for mounting the semiconductor chip.
- The second substrate is positioned at a distance from the first substrate.
- The wire connects the first substrate to the second substrate.
- The mold structure covers the top surface of the semiconductor chip, as well as the lateral surfaces of the chip and the wire.
- The under-fill pattern is located on the lateral surface of the wire and is positioned between the wire and the mold structure.
Potential applications of this technology:
- Semiconductor packaging industry
- Electronics manufacturing
Problems solved by this technology:
- Provides a protective mold structure for the semiconductor chip and wire connections
- Ensures proper electrical connections between the substrates
- Prevents damage to the semiconductor chip and wire during handling and operation
Benefits of this technology:
- Enhanced protection for the semiconductor chip and wire connections
- Improved reliability and durability of the semiconductor package
- Facilitates efficient electrical connections between substrates
Original Abstract Submitted
A semiconductor package includes a first substrate, a semiconductor chip on the first substrate, a second substrate spaced apart from the first substrate, a wire spaced apart from a lateral surface of the semiconductor chip and connecting the first substrate to the second substrate, a mold structure on a top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and a lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire and is between the wire and the mold structure.
