18447856. Memory Device With Source Lines in Parallel simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

Memory Device With Source Lines in Parallel

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Ku-Feng Lin of New Taipei City (TW)

Memory Device With Source Lines in Parallel - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447856 titled 'Memory Device With Source Lines in Parallel

Simplified Explanation

The abstract describes a memory device that consists of a memory cell array with multiple memory cells organized in rows and columns. Each row is associated with a word line, and each column is associated with a bit line and a source line. Each memory cell includes a storage device connected to the bit line, which can be switched between two resistance states based on the bit line signal. The memory cell also includes a selection device connected in series with the storage device and coupled to the source line, providing access to the storage device in response to a word line signal. The memory device also includes a word-line driver and a bit-line driver, and a number of source lines are connected in parallel.

• The memory device has a memory cell array organized in rows and columns.
• Each memory cell includes a storage device and a selection device.
• The storage device can be switched between two resistance states based on the bit line signal.
• The selection device provides access to the storage device in response to the word line signal.
• The memory device includes a word-line driver and a bit-line driver.
• Multiple source lines are connected in parallel.

Potential applications of this technology:

• Memory devices in computers, smartphones, and other electronic devices.
• Storage devices in data centers and cloud computing systems.
• Embedded memory in microcontrollers and IoT devices.

Problems solved by this technology:

• Efficient storage and retrieval of data in memory devices.
• Reduction of power consumption in memory operations.
• Increased speed and reliability of memory access.

Benefits of this technology:

• Higher memory density due to the organization of memory cells in rows and columns.
• Faster data access and retrieval with the use of word-line and bit-line drivers.
• Lower power consumption compared to traditional memory technologies.
• Improved reliability and durability of memory cells.

Original Abstract Submitted

A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.