LOW-RESISTANCE VIA STRUCTURES

Organization Name

intel corporation

Inventor(s)

Ming-Yi Shen of Portland OR (US)

Chi-Hing Choi of Portland OR (US)

Jaladhi Mehta of Beaverton OR (US)

Tofizur Rahman of Portland OR (US)

Payam Amin of Portland OR (US)

Justin E. Mueller of Portland OR (US)

Vincent Hipwell of Hillsboro OR (US)

Cortnie S. Vogelsberg of Beaverton OR (US)

Shivani Falgun Patel of Hillsboro OR (US)

LOW-RESISTANCE VIA STRUCTURES

This abstract first appeared for US patent application 20250006592 titled 'LOW-RESISTANCE VIA STRUCTURES

Original Abstract Submitted

techniques to form low-resistance vias are discussed. in an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. the via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. the conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. the conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.