18340665. DATA RECEIVER CIRCUIT INCLUDING LOOP-UNROLLED PHASE DECISION FEEDBACK EQUALIZER WITH DUTY CYCLE CONTROL (QUALCOMM Incorporated)
Contents
DATA RECEIVER CIRCUIT INCLUDING LOOP-UNROLLED PHASE DECISION FEEDBACK EQUALIZER WITH DUTY CYCLE CONTROL
Organization Name
Inventor(s)
Seokkyun Ko of San Diego CA (US)
Ashwin Sethuram of San Clemente CA (US)
Jeffrey Mark Hinrichs of San Diego CA (US)
DATA RECEIVER CIRCUIT INCLUDING LOOP-UNROLLED PHASE DECISION FEEDBACK EQUALIZER WITH DUTY CYCLE CONTROL
This abstract first appeared for US patent application 18340665 titled 'DATA RECEIVER CIRCUIT INCLUDING LOOP-UNROLLED PHASE DECISION FEEDBACK EQUALIZER WITH DUTY CYCLE CONTROL
Original Abstract Submitted
A data signal receiver circuit, including: a comparator configured to generate a first data signal based on a comparison of an input data signal and a reference voltage, wherein the first data signal includes a first logic low pulse and a first logic high pulse; and a duty cycle control circuit configured to generate: a second data signal based on the first data signal, wherein the second data signal includes a second logic low pulse responsive to the first logic low pulse, wherein the second logic low pulse has a width greater than a unit interval (UI); and a third data signal based on the first data signal, wherein the third data signal includes a second logic high pulse responsive to the first logic high pulse, wherein the second logic high pulse has a width greater than the UL.
