18338070. SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM (QUALCOMM Incorporated)
SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM
Organization Name
Inventor(s)
Surendra Paravada of Hyderabad (IN)
Madhu Yashwanth Boenapalli of Hyderabad (IN)
Vinod Kumar Kuruma of Jogulamba Gadwal (IN)
Sai Praneeth Sreeram of Anantapur (IN)
Ravindranath Doddi of Hyderabad (IN)
SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM
This abstract first appeared for US patent application 18338070 titled 'SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM
Original Abstract Submitted
A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced latency and improved performance by reconfiguring the PCIe link to use an increased number of lanes for retransmitting data packets held in a replay buffer if one or more data packets transmitted by the TX device are flagged as not acknowledged (NACK) by the RX device. Before retransmitting the NACK-flagged packet(s), the link is reconfigured to use a greater number of lanes, preferably the maximum number of lanes that are available for use, and then the NACK-flagged packet(s) is retransmitted using the greater number of lanes until successful receipt of the NACK-flagged packets has been acknowledged by the RX device. Once the NACK-flagged packet(s) is successfully received by the RX device, the link is reconfigured to use the previous number of lanes and operations of the link resume using the previous number of lanes.
