18338653. APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK STATE TRANSITIONS WITHIN DIE INTERCONNECT ARCHITECTURES (QUALCOMM Incorporated)
APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK STATE TRANSITIONS WITHIN DIE INTERCONNECT ARCHITECTURES
Organization Name
Inventor(s)
Santhosh Reddy Akavaram of Hyderabad (IN)
Prakhar Srivastava of Lucknow (IN)
Sridhar Anumala of Hyderabad (IN)
Ramacharan Sundararaman of San Jose CA (US)
Sonali Jabreva of Firozabad (IN)
Khushboo Kumari of Hyderabad (IN)
APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK STATE TRANSITIONS WITHIN DIE INTERCONNECT ARCHITECTURES
This abstract first appeared for US patent application 18338653 titled 'APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK STATE TRANSITIONS WITHIN DIE INTERCONNECT ARCHITECTURES
Original Abstract Submitted
Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.
