18339529. PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-BASED DEVICES (QUALCOMM Incorporated)
Contents
PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-BASED DEVICES
Organization Name
Inventor(s)
Akilesh Krishnamurthy of San Jose CA (US)
Conrado Blasco of San Mateo CA (US)
Paul Kitchin of Austin TX (US)
Aniket Bhivasen Bhor of Santa Clara CA (US)
PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-BASED DEVICES
This abstract first appeared for US patent application 18339529 titled 'PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-BASED DEVICES
Original Abstract Submitted
Providing physical register (PR) swap memory renaming in processor-based devices is disclosed herein. In some exemplary aspects, a processor provides an instruction processing circuit comprising a scheduling stage circuit and an execution stage circuit. The scheduling stage circuit comprises a reservation station circuit, while the execution stage circuit comprises a PR swap table storing a plurality of PR swap table entries. The scheduling stage circuit issues a first instruction that is associated with a store dependency ID. The execution stage circuit, in response to the issuing of the first instruction, identifies a PR swap table entry among the plurality of PR swap table entries corresponding to the store dependency ID, retrieves a load dependency ID of the PR swap table entry, and broadcasts the load dependency ID to the reservation station circuit to wake a second instruction that is associated with the load dependency ID.
