18626645. HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP (QUALCOMM Incorporated)
Contents
HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP
Organization Name
Inventor(s)
Vinod Chamarty of Campbell CA (US)
Sagar Koorapati of Longview TX (US)
Alon Naveh of Corte Madera CA (US)
HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP
This abstract first appeared for US patent application 18626645 titled 'HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP
Original Abstract Submitted
Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.
