18626683. TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM (QUALCOMM Incorporated)
TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM
Organization Name
Inventor(s)
Vinod Chamarty of Campbell CA (US)
Sagar Koorapati of Longview TX (US)
Sreeram Jayadev of Austin TX (US)
Alon Naveh of Corte Madera CA (US)
TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM
This abstract first appeared for US patent application 18626683 titled 'TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM
Original Abstract Submitted
Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.
