Intel corporation (20240427975). METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO VALIDATE TIMING CONSTRAINTS FOR AN INTEGRATED CIRCUIT
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO VALIDATE TIMING CONSTRAINTS FOR AN INTEGRATED CIRCUIT
Organization Name
Inventor(s)
Rakesh Kandula of Bangalore (IN)
Srinivasa Ramakrishna Stg of Bangalore (IN)
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO VALIDATE TIMING CONSTRAINTS FOR AN INTEGRATED CIRCUIT
This abstract first appeared for US patent application 20240427975 titled 'METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO VALIDATE TIMING CONSTRAINTS FOR AN INTEGRATED CIRCUIT
Original Abstract Submitted
methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. an example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (soc) architecture, obtain a timing assertion associated with the soc architecture, determine, using a formal property verification (fpv) tool, valid functional vectors and counter examples for the soc architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.
